1
Gertjan Hemink, Yupin Fong: Programming non-volatile memory. Sandisk Corporation, Vierra Magen Marcus Harmon & DeNiro, May 3, 2005: US06888758 (183 worldwide citation)

One or more programming operations are performed on a set of non-volatile storage elements. For example, the programming operations may include applying a set of programming pulses. A verify process is performed to determine which of the non-volatile storage element have reached an intermediate veri ...


2
Kevin M Conley, Yoram Cedar: Pipelined parallel programming operation in a non-volatile memory system. SanDisk Corporation, Parsons Hsue & de Runtz, March 22, 2005: US06871257 (151 worldwide citation)

The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is bus ...


3
Sergey Anatolievich Gorobets: Memory system sectors. Lexar Media, Law Offices of Imam, May 24, 2005: US06898662 (118 worldwide citation)

An embodiment of the present invention includes a method of implementing the logical grouping of memory system sectors in a non-volatile memory system in order to increase the operational speed of the memory system, the method comprising allocating sets of contiguous logical sectors containing file ...


4
Guy Cohen: Method circuit and system for determining a reference voltage. Aifun Semiconductors, Eitan Law Group, November 8, 2005: US06963505 (117 worldwide citation)

The present invention is a method, circuit and system for determining a reference voltage. Some embodiments of the present invention relate to a system, method and circuit for establishing a set of operating reference cells to be used in operating (e.g. reading) cells in an NVM block or array. As pa ...


5
Kevin M Conley, Daniel C Guterman, Carlos J Gonzalez: Method and structure for efficient data verification operation for non-volatile memories. SanDisk Corporation, Parsons Hsue & de Runtz, December 6, 2005: US06972993 (107 worldwide citation)

An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data v ...


6
Sau Ching Wong: Parallel programming of multiple-bit-per-cell memory cells on a continuous word line. Multi Level Memory Technology, David T Millers, April 19, 2005: US06882567 (106 worldwide citation)

Write operations that simultaneously program multiple memory cells on the same word line in an MBPC Flash memory employ word line voltage variation, programming pulse width variation, and data-dependent bit line and/or source line biasing to achieve uniform programming accuracy across a range of tar ...


7
Chih Hsin Wang, Bing Yeh: Method of operating a semiconductor memory array of floating gate memory cells with horizontally oriented edges. Silicon Storage Technology, DLA Piper Rudnick Gray Cary US, April 19, 2005: US06882572 (94 worldwide citation)

A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region i ...


8
Koji Hosono: Non-volatile semiconductor memory device and electric device with the same. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, November 22, 2005: US06967874 (85 worldwide citation)

A non-volatile semiconductor memory device includes: a cell array having electrically rewritable and non-volatile memory cells disposed at the respective intersections of word lines and bit lines intersecting each other; a row decoder circuit for selectively driving a word line of the cell array; a ...


9
Frankie F Roohparvar: NAND flash memory with improved read and verification threshold uniformity. Micron Technology, Leffert Jay & Polglaze PA, December 13, 2005: US06975542 (76 worldwide citation)

A plurality of cells in a flash memory device are coupled together in a series configuration, as in a NAND flash memory. A position of a first accessed cell is determined with reference to a ground potential in the flash memory device. A first word line signal is coupled to the first accessed cell. ...


10
Toshitake Yaegashi, Akira Goda, Mitsuhiro Noguchi: Nonvolatile semiconductor memory device. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, May 17, 2005: US06894931 (71 worldwide citation)

A cell array is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on a semiconductor substrate. Each of the memory cells has a charge accumulation layer formed via a first gate insulating film and a gate electrode formed on the charge accumulation layer v ...