1
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John G Favor, Dale R Greenley, Robert A Cargnoni: Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags. Nexgen Microsystems, Townsend and Townsend Khourie and Crew, July 6, 1993: US05226126 (369 worldwide citation)

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report terminat ...


2
William M Johnson: System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache. Advanced Micro Devices, Foley & Lardner, August 4, 1992: US05136697 (274 worldwide citation)

A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate the address ...


3
John G Favor, Korbin Van Dyke, David R Stiles: Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency. NexGen Microsystems, Townsend and Townsend Khourie and Crew, July 6, 1993: US05226130 (260 worldwide citation)

The present invention provides for the updating of both the instructions in a branch prediction cache and instructions recently provided to an instruction pipeline from the cache when an instruction being executed attempts to change such instructions ("Store-Into-Instruction-Stream"). The branch pre ...


4
William M Johnson: Multiple instruction decoder for minimizing register port requirements. Advanced Micro Devices, Foley & Lardner, July 7, 1992: US05129067 (220 worldwide citation)

A multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read port contentions by the N register-operand ide ...


5
Quentin E Dolecek: Memory-linked wavefront array processor. The Johns Hopkins University, Robert E Archibald, Howard W Califano, January 19, 1988: US04720780 (219 worldwide citation)

A Memory-Linked Wavefront Array Processor (MWAP) is disclosed which computes a broad range of signal processing, scientific and engineering problems at ultra-high speed. The memory-linked wavefront array processor is an array of identical programmable processing elements linked together by dual-port ...


6
Kenichi Kaki, Kunihiro Katayama, Takashi Tsunehiro: Semiconductor storage device including a controller for continuously writing data to and erasing data from a plurality of flash memories. Hitachi, Antonelli Terry Stout & Kraus, June 25, 1996: US05530828 (208 worldwide citation)

A semiconductor storage device such as a disk pack includes a plurality of flash memories, a write buffer memory in which data are temporarily held, a processor which controls data writing and erasing operations and which transfers and analyzes commands and statuses to and from the flash memories, a ...


7
Michael H Branigin: Computer processor with an efficient means of executing many instructions simultaneously. November 28, 1995: US05471593 (206 worldwide citation)

To increase the performance of a pipelined processor executing instructions, conditional instruction execution issues and executes instructions, including but not limited to branches, before the controlling conditions may be available and makes the decision to update the destination as late as possi ...


8
Bodo Parady: Thread switch on blocked load or store using instruction thread field. Sun Microsystems, Townsend and Townsend and Crew, August 3, 1999: US05933627 (205 worldwide citation)

A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers ...


9
Steven G Morton: DSP having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word. Harry F Smith, October 13, 1998: US05822606 (191 worldwide citation)

The Parallel DSP Chip has a general purpose, reduced instruction set for parallel digital signal processing. The following pertains to the preferred embodiment. Most instruction words are 32 bits long and execute at the rate of one per clock cycle. Each instruction word is executed by a single, pipe ...


10
David B Fite, John E Murray, Dwight P Manley, Michael M McKeon, Elaine H Fite, Ronald M Salett, Tryggve Fossum: Branch prediction. Digital Equipment Corporation, Arnold White & Durkee, August 25, 1992: US05142634 (188 worldwide citation)

A branch prediction is made by searching a cache memory for branch history information associated with a branch instruction. If associated information is not found in the cache, then the branch is predicted based on a predetermined branch bias for the branch instruction's opcode; otherwise, the bran ...



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