Hideaki Matsuo, Yuji Takata, Terutaka Teshima, Seiji Igi, Shan Lu, Kazuyuki Imagawa: Hand gesture recognizing device. Matsushita Electric Industrial, Communications Research Laboratory of Ministry of Posts and Telecommunications, Wenderoth Lind & Ponack, April 10, 2001: US06215890 (482 worldwide citation)

A hand gesture recognizing device is provided which can correctly recognize hand gestures at high speed without requiring users to be equipped with tools. A gesture of a user is stereoscopically filmed by a photographing device

Michael J Black, Yaser Yacoob: Apparatus and method for tracking facial motion through a sequence of images. Xerox Corporation, September 1, 1998: US05802220 (278 worldwide citation)

A system tracks human head and facial features over time by analyzing a sequence of images. The system provides descriptions of motion of both head and facial features between two image frames. These descriptions of motion are further analyzed by the system to recognize facial movement and expressio ...

Alicia Gonzalez Acebo, Christopher David Frawley: Pre- and post-ticketed travel reservation information management system. Amadeus Global Travel Distribution, Jenkens & Gilchrist A Professional Corporation, February 8, 2000: US06023679 (146 worldwide citation)

Methods and system for effecting the instantaneous data transmission to a locally operated computer system upon an occurrence in the computer reservation system (CRS). Specifically, a method for automatically generating pre-ticketed travel information is disclosed, in which booked reservation inform ...

Hidekazu Matsumoto, Tadaaki Bandoh, Hideo Maejima: Data processing unit with pipelined operands. Hitachi, Antonelli Terry & Wands, June 12, 1984: US04454578 (126 worldwide citation)

A data processing unit for executing variable length instructions in which operand specifiers for specifying addressing modes of operands are independent from operation codes for ascertaining operations is disclosed. An instruction fetch unit includes an instruction buffer for prefetching and retain ...

Phillip D Hester, Richard O Simpson: Virtual memory address translation mechanism with combined hash address table and inverted page table. International Business Machines Corporation, J B Kraft, Thomas E Tyson, July 14, 1987: US04680700 (100 worldwide citation)

A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memory wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion ...

John E Zolnowsky, Charles L Whittington, William M Keshlear: Memory management unit. Motorola, Anthony J Sarli Jr, Jeffrey Van Myers, September 25, 1984: US04473878 (93 worldwide citation)

A memory management unit of use in a memory management system. The memory management unit selectively maps a logical address to a respective physical address in accordance with a selected one of a plurality of segment descriptors, each of which defines a logical-to-physical address mapping and a ran ...

William D Strecker, Thomas N Hastings, Richard F Lary, David P Rodgers, Steven H Rothman: Central processor unit for executing instructions of variable length. Digital Equipment Corporation, Cesari & McKenna, November 25, 1980: US04236206 (93 worldwide citation)

A digital data processing system with a central processor for responding to diverse instructions characterized by having variable length. Each instruction includes an operation code. Certain instructions also include one or more operand specifiers. Each operand specifier can comprise one or more dat ...

Lawrence H Katz, Douglas M Wells, Michael S Richmond, Richard A Belgard, Walter A Wallach Jr, David H Bernstein, John K Ahlstrom, John F Pilat, David A Farber, Richard G Bratt: Method of performing a call operation in a digital data processing system having microcode call and return operations. Data General Corporation, Gordon E Nelson, Joel Wall, Jacob Frank, January 8, 1985: US04493027 (77 worldwide citation)

A method for executing call and return instructions in a digital computer system operating under control of microcode. The microcode may specify calls to and returns from sequences of microinstructions. A call microinstruction sequence corresponds to the call instruction. The call microcode in turn ...

Robert P Fletcher: Second level cache replacement method and apparatus. International Business Machines Corporation, Bernard M Goldman, August 7, 1984: US04464712 (77 worldwide citation)

The disclosure controls the replacement selection of entries in a second level (L2) cache directory of a storage hierarchy using replaced and hit addresses of a dynamic look-aside translation buffer (DLAT) at the first level (L1) in the hierarchy which receives CPU storage requests along with the CP ...

Justin R Butwell, Casper A Scalzi, Richard J Schmalz: Address generating mechanism for multiple virtual spaces. International Business Machines, Bernard M Goldman, October 19, 1982: US04355355 (58 worldwide citation)

The detailed embodiment associates access registers (AR's) with the general purpose registers (GPR's) in a data processor. The AR's are each loaded with a unique STD (segment table descriptor). The STD comprises a segment table address in main storage and a segment table length field. There are 15 A ...