Sagy Pundak Mintz
Sagy P Mintz, Alexander D Deitz: Distribution of electronic market data. Trading Technologies International, McDonnell Boehnen Hulbert & Berghoff, December 30, 2014: US08924286

A system and method are provided that, among other things, can reduce the burden on receiving computers, increase data throughput, reduce system failure, and provide components of a scalable and flexible network architecture. Specifically, the system and method provide a multichannel-multicast netwo ...

Henry L Scantlin: RISC architecture computer configured for emulation of the instruction set of a target computer. International Meta Systems, Freilich Hornbaker Rosen, November 12, 1996: US05574927 (247 worldwide citation)

A RISC architecture computer configured for emulating the instruction set of a target computer to execute software written for the target computer, e.g., an Intel 80X86, a Motorola 680X0 or a MIPS R3000. The apparatus is integrated with a core RISC computer to form a RISC computer that executes an e ...

Ashish A Pandya: Runtime adaptable search processor. Armstrong Teasdale, March 23, 2010: US07685254 (239 worldwide citation)

A runtime adaptable search processor is disclosed. The search processor provides high speed content search capability to meet the performance need of network line rates growing to 1 Gbps, 10 Gbps and higher. The search processor provides a unique combination of NFA and DFA based search engines that ...

James S Blomgren: Dual-architecture super-scalar pipeline. Exponential Technology, Stuart T Auvinen, January 28, 1997: US05598546 (230 worldwide citation)

A dual-instruction-set processor processes instructions from two or more instruction sets. The processor has several pipelines for processing different types of operations--Memory, ALU, and Branch operations. Instructions are decoded by RISC and CISC instruction decoders which generate control words ...

William M Johnson: Multiple instruction decoder for minimizing register port requirements. Advanced Micro Devices, Foley & Lardner, July 7, 1992: US05129067 (220 worldwide citation)

A multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read port contentions by the N register-operand ide ...

William N Joy, Marc Tremblay, Gary Lauterbach, Joseph I Chamdani: Thread switch logic in a multiple-thread processor. Sun Microsystems, Ken J Koestner, Skjerven Morrill MacPherson, January 22, 2002: US06341347 (212 worldwide citation)

A processor includes a thread switching control logic that performs a fast thread-switching operation in response to an L

Valeri Popescu, Merle A Schultz, Gary A Gibson, John E Spracklen, Bruce D Lightner: Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched. Townsend and Townsend and Crew, January 23, 1996: US05487156 (177 worldwide citation)

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if ...

James L Taylor: SIMD array processor with global instruction control and reprogrammable instruction decoders. International Business Machines Corporation, Michael J Scheer, John D Crane, Robert L Troike, February 12, 1991: US04992933 (154 worldwide citation)

A single-instruction-multiple-data (SIMD) array processor is described with a multi-dimensional array of processing elements and control logic for issuing global instructions to the array. Each processing element in the array has individually programmable instruction decoder and a mechanism which en ...

Korbin S Van Dyke, Paul Campbell, Don Alan Van Dyke: Computer for execution of RISC and CISC instruction sets. ATI International, David E Boundy, Willkie Farr & Gallagher, May 16, 2006: US07047394 (147 worldwide citation)

A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instruction ...

Gary N Hammond, Kevin C Kahn, Donald B Alpert: Processor capable of executing programs that contain RISC and CISC instructions. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 10, 1997: US05638525 (147 worldwide citation)

A data processor is described. The data processor is capable of decoding and executing the first instruction of a first instruction set and the second instruction of a second instruction set wherein the first instruction and the second instruction originate from a single computer program. Alternativ ...