1
Seymour R Cray Jr: Computer vector register processing. Cray Research, Merchant Gould Smith Edell Welter & Schmidt, December 5, 1978: US04128880 (269 worldwide citation)

Vector processing in a computer is achieved by means of a plurality of vector registers, a plurality of independent fully segmented functional units, and means for controlling the operation of the vector registers. Operations are performed on data from vector register to functional unit and back to ...


2
Peter Willy Markstein, Alan Levi Tritter: Hierarchical security mechanism for dynamically assigning security levels to object programs. International Business Machines Corporation, Roy R Schlemmer Jr, August 1, 1978: US04104721 (138 worldwide citation)

A computer system organization which allows a program to specify a predetermined security level for other programs which it invokes, while at the same time being subject to security restraints placed on it either by a higher priority level invoking program or by the operating system. A plurality of ...


3
Maxwell C Gilliland, Burton J Smith, Gary L Ferguson: Concurrent task and instruction processor and method. Denelcor, O Rourke & Harris, October 21, 1980: US04229790 (123 worldwide citation)

A processor and method for concurrent processing of tasks and instructions are disclosed. The processor is basically a multiple instruction, multiple data stream (MIMD) digital computer that utilizes pipelining for control and function units, but avoids precedence constraint penalties. Task and inst ...


4
Marc Appell, Georges Lepicard, Philippe Hubert de Rivet, John J Bradley, Benjamin S Franklin: Protection of data in an information multiprocessing system by implementing a concept of rings to represent the different levels of privileges among processes. Compagnie Internationale pour l Informatique CII Honeywell Bull, Diller Ramik & Wight, December 4, 1979: US04177510 (117 worldwide citation)

Computer data and procedure protection by preventing processes from intering with each other or sharing each other's address space in an unauthorized manner is accomplished in hardware/firmware by restricting addressability to a segmented memory and by a ring protection mechanism.


5
Patrick Dufond, Jean Claude Cassonnet, Jean Louis Bogaert, Philippe Hubert DE Rivet, John J Bradley, Benjamin S Franklin: Process management structures and hardware/firmware control. Compagnie Honeywell Bull, Nicholas Prasinos, Ronald T Reiling, April 11, 1978: US04084228 (113 worldwide citation)

A system and method for computer process dispatching in a multiprogramming/multiprocessing environment is disclosed. Each process in the multiprogramming/multiprocessing computer system may be in one of four states at any given time as follows:


6
Frank E Heart, Severo M Ornstein, William B Barker, William R Crowther: Multiprocessor computer apparatus employing distributed communications paths and a passive task register. Bolt Beranek and Newman, Kenway & Jenney, December 19, 1978: US04130865 (91 worldwide citation)

Computer apparatus which employs a plurality of processing units, a memory unit, and a communication unit, each of the units including a data transfer bus. A bus coupler is provided between each pair of units of differing type to form a distributed data communications network. An addressable, passiv ...


7
Charles A Milligan, Edwin R Videki II, Winston F Yates: Buffered peripheral subsystems. International Business Machines Corporation, H F Somermeyer, March 6, 1984: US04435762 (87 worldwide citation)

A peripheral device subsystem enables its peripheral devices to operate asynchronously with respect to attaches hosts through the use of managed buffers, new multiple data transfer modes, control and error recovery operations. In a preferred first or buffer mode of operation, all data of each record ...


8
Robert J Frankenberg: Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system. Hewlett Packard Company, A C Smith, David A Boone, June 7, 1977: US04028675 (85 worldwide citation)

A multi-module, multi-port memory system includes modules having semiconductor memory circuits which require periodic refreshing to retain the contents stored therein. Priority circuits resolve conflicts between the multi-port access of the memory modules and the refreshing requirements of semicondu ...


9
Robert F Monaco, Nicholas Derchak: Apparatus for processing interrupts in microprocessing systems. Sperry Rand Corporation, B Franklin Griffin Jr, July 5, 1977: US04034349 (82 worldwide citation)

Circuitry external of a microprocessor determines priority between different peripheral devices requesting interrupts to generate a restart vector and a signal granting priority to one of the interrupt-requesting devices. The peripheral device loads its status and address into two addressable regist ...


10
Shigeo Nagashima, Shunichi Torii, Koichiro Omoda, Yasuhiro Inagami: Data processing system including scalar data processor and vector data processor. Hitachi, Antonelli Terry & Wands, September 10, 1985: US04541046 (78 worldwide citation)

A vector processor comprises a main storage for storing scalar instruction chains and vector instruction chains for executing desired operations, and a scalar processing unit and a vector processing unit for separately fetching the scalar instruction chains and the vector instruction chains, decodin ...