1
James Kraemer Ph.D.
Robert L Angell, David W Cosby, Robert R Friedlander, James R Kraemer: Processor cooling management. International Business Machines Corporation, Yee & Associates P C, John R Pivnichny, September 9, 2014: US08831791 (1 worldwide citation)

Illustrative embodiments provide a computer implemented method, a data processing system, and a computer program product for adjusting cooling settings. The computer implemented method comprises analyzing a set of instructions of an application to determine a number of degrees by which a set of inst ...


2
James Kraemer Ph.D.
Robert Lee Angell, David Wayne Cosby, Robert R Friedlander, James R Kraemer: Processor cooling management. International Business Machines Corporation, Yee & Associates P C, John R Pivnichny, November 13, 2012: US08311683 (1 worldwide citation)

Illustrative embodiments provide a computer implemented method, a data processing system, and a computer program product for adjusting cooling settings. The computer implemented method comprises analyzing a set of instructions of an application to determine a number of degrees by which a set of inst ...


3
Private
Susan K Candelaria, Scott M Carlson, Daniel F Casper, John R Flanagan, Roger G Hathorn, Matthew J Kalos, Louis W Ricci, Dale F Riedy, Gustav E Sittmann III: Facilitating transport mode input/output operations between a channel subsystem and input/output devices. International Business Machines Corporation, Cantor Colburn, Steven Chiu, October 1, 2013: US08549185

A computer program product is provided for performing an input/output (I/O) processing operation at a host computer system. The computer program product is configured to perform: obtaining a transport command word (TCW) at a channel subsystem for an I/O operation, the TCW including an address of a t ...


4
Masataka Fujisaki: Auction information transmission processing. Flex Japan, Aucnet, Armstrong Nikaido Marmelstein & Kubovcik, December 6, 1988: US04789928 (770 worldwide citation)

An auction information transmission processing system is constructed by connecting a most significant front computer to a host computer, arranging at least one stage of a plurality of intermediate front computers and a plurality of least significant front computers so as to be connectable to the mos ...


5
Robert F Hartmann, Yiu Fai Chan, Robert Frankovich, Jung Hsing Ou: Programmable logic array device using EPROM technology. Altera Corporation, Hamrick Hoffman Guillot & Kazubowski, September 2, 1986: US04609986 (334 worldwide citation)

An electrically programmable, eraseable and reprogrammable, monolithic integrated circuit logic array device is disclosed. The device includes a plurality of three types of logic array macrocells, each including an AND array matrix of EPROM transistors configured to form a plurality of "product term ...


6
Vincent Boston: Portable financial transaction card capable of authorizing a transaction in foreign currencies. VISA International Service Association, Limbach Limbach & Sutton, August 23, 1988: US04766293 (333 worldwide citation)

A transaction card is disclosed capable of authorizing a transaction in a foreign currency. The subject transaction card includes an internal microprocessor which is connected to a memory. Stored within the memory is a transaction limit associated with each account of the cardholder. Also stored in ...


7
Ross H Freeman, Hung Cheng Hsieh: Distributed memory architecture for a configurable logic array and method for using distributed memory. Xilinx, Edel M Young, Patrick T Bever, August 30, 1994: US05343406 (252 worldwide citation)

Additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array ...


8
Ralph D Wittig, Sundararajarao Mohan, Richard A Carberry: FPGA configurable logic block with multi-purpose logic/memory circuit. Xilinx, Patrick T Bever Hoffman & Harms Bever Esq, Lois D Cartier, November 21, 2000: US06150838 (247 worldwide citation)

A logic/memory circuit (LMC) utilized in a configurable logic block (CLB) of a programmable logic device (PLD) that implements an eight-input lookup table (LUT) using an array of programmable elements arranged in rows and columns. A decoder is used to read bit values from one column (e.g., sixteen p ...


9
Bernard J New: Dedicated function fabric for use in field programmable gate arrays. Xilinx, Bever Hoffman & Harms, February 12, 2002: US06346824 (196 worldwide citation)

A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of dedicated function blocks. The CLEs can be operated as conventional configurable logic elements, completely disconnected from the arr ...


10
David P Schultz, Lawrence C Hung, F Erich Goetting: Method and structure for configuring FPGAS. Xilinx, Patrick T Bever Esq, Lois D Cartier, Bever Hoffman & Harms, March 20, 2001: US06204687 (193 worldwide citation)

An FPGA configuration circuit including a bus interface for applying a bit stream from either a JTAG interface or an input/output block (IOB) interface onto a bus. The bus interface parses a header word from the bit stream into an address field and an operand field. Several registers are connected t ...