1
Brent Keeth: Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same. Micron Technology, Dorsey & Whitney, February 22, 2000: US06029250 (375 worldwide citation)

A method and circuit adaptively adjust the timing offset of a digital signal relative to a clock signal output coincident with that digital signal to enable a latch receiving the digital signal to store the digital signal responsive to the clock signal. The digital signal is applied to the latch, an ...


2
LaVaughn F Watts Jr, Steven J Wallace: Real-time power conservation for portable computers. Texas Instruments, Ronald O Neerings, James C Kesterson, Richard L Donaldson, June 8, 1993: US05218704 (242 worldwide citation)

A real-time power conservation apparatus and method for portable computers employs a monitor to determine whether a CPU may rest based upon a real-time sampling of the CPU activity level and to activate a hardware selector to carry out the monitor's determination. If the monitor determines the CPU m ...


3
Michael N Day: System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur. International Business Machines Corporation, Joseph F Villella Jr, H St Julian, July 25, 1989: US04851987 (219 worldwide citation)

An apparatus and method are provided for disabling the clocking of a processor in a battery operated computer during non-processing times. The clocking is disabled at the conclusion of a processing operation. The clocking can then be re-enabled using interrupts from any one of a plurality of sources ...


4
Joseph M Jeddeloh: Timing circuit for high speed memory. Micron Technology, Trop Pruner & Hu P C, June 4, 2002: US06401213 (199 worldwide citation)

A timing circuit to adjust a data strobe signal received from a synchronous memory includes a delay circuit to adjustably delay the data strobe signal and to generate a delayed data strobe signal, a clock capture register to sample the delayed data strobe signal and to generate a sampled clock signa ...


5
Brent Keeth: Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same. Micron Technology, Dorsey & Whitney, August 6, 2002: US06430696 (172 worldwide citation)

A bus capture circuit captures digital signals applied on respective lines of a bus. The bus capture circuit includes a clock delay circuit that generates an internal clock signal responsive to an external clock signal. The internal clock signal has a fixed delay relative to the external clock signa ...


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Donald L Tietjen: Wait mode power reduction system and method for data processor. Motorola, John A Fisher, Jeffrey Van Myers, Jonathan P Meyer, October 25, 1988: US04780843 (155 worldwide citation)

A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal i ...


8
James Herman Scheuneman: Conditional bypass of error correction for dual memory access time selection. Sperry Rand Corporation, Kenneth T Grace, William E Cleaver, Marshall M Truex, September 5, 1978: US04112502 (155 worldwide citation)

A method of and an apparatus for conditionally bypassing the error correction function of a large scale integrated (LSI) semiconductor random access memory (RAM) is disclosed. A content addressable memory (CAM) is utilized to store the addresses of the addressable locations in the RAM in which an er ...


9
Joseph M Jeddeloh, Jeffrey J Rooney, Richard F Nicholson, Dean A Klein: Memory controller with low skew control signal. Micron Electronics, November 25, 1997: US05692165 (148 worldwide citation)

An apparatus and a method are provided for delaying or skewing a control signal provided to an electronic device such as a memory device with an alignment delay, such that the overall delay associated with the alignment delay and the propagation delay associated with outputting the control signal to ...


10
Walter L Davis, Barry W Herold, Wendell L Little: Synthesized clock microcomputer with power saving. Motorola, Vincent B Ingrassia, Anthony J Sarli Jr, January 9, 1990: US04893271 (144 worldwide citation)

A microcomputer having predetermined clock pulse frequency requirements receives pulses from a multiplying type frequency synthesizer which utilizes a reference frequency less than the largest of the predetermined requirements. The synthesizer is responsive to program instructions to generate clock ...