61
James V Crouse, Terry M Lowe, Limin Miao, James R Montstream, Norbert Vogl, Colleen A Wyckoff: Method for comprehensively verifying design rule checking runsets. International Business Machines Corporation, Richard M Kotulak Esq, McGinn & Gibb PLLC, May 4, 2004: US06732338 (202 worldwide citation)

A system and method for automatically creating testcases for design rule checking comprises first creating a table with a design rule number, a description, and the values from a design rule manual. Next, any design specific options are derived that affect the flow of the design rule checking, inclu ...


62
William Wai Yan Ho: Layer-based rule checking for an integrated circuit layout. Synopsys, Wagner Murabito & Hao, April 23, 2002: US06378110 (202 worldwide citation)

A computer implemented method for verifying a physical layout of an integrated circuit design for a semiconductor chip. The physical layout is specified in terms of a plurality of layers used to fabricate the chip. Initially, a pre-defined set of rules are stored in memory. These rules are used to s ...


63
Michel Luc Côté, Philippe Hurat, Christophe Pierrat: Method and apparatus for facilitating process-compliant layout optimization. Numerical Technologies, Park Vaughan & Fleming, June 1, 2004: US06745372 (201 worldwide citation)

One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the repres ...


64
Rajiv Kapur: Poly routing for chip interconnects with minimal impact on chip performance. LSI Logic Corporation, Mitchell Silberberg & Knupp, May 29, 2001: US06240542 (200 worldwide citation)

Methods for using the polysilicon layer to route the cells in the ASIC are disclosed. The poly layer of an IC chip is used for routing chip interconnects with minimal impact on the chip performance by selecting nets in the IC chip based on a predetermined or a desired qualification. A maximum allowa ...


65
Ravi Varadarajan, Robert Thompson: Optimized placement and routing of datapaths. Cadence Design Systems, Fenwick & West, November 17, 1998: US05838583 (199 worldwide citation)

A computer system, method and software product enables automatic placement and routing of datapath functions using a design methodology that preserves hiearchical and structural regularity in top down designs for datapaths. The system includes a datapath floorplanner, a datapath placer, and routing ...


66
David White, Taber H Smith: Test masks for lithographic and etch processes. Praesagus, Bingham McCutchen, July 10, 2007: US07243316 (198 worldwide citation)

A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated ...


67
Michel L Côté, Christophe Pierrat: Standard cell design incorporating phase information. Synopsys, Bever Hoffman & Harms, Jeannette S Harms, April 11, 2006: US07028285 (197 worldwide citation)

Phase information is incorporated into a cell-based design methodology. Standard cells have four edges: top, bottom, left, and right. The top and bottom edges have fixed phase shifters placed, e.g. 0. A given cell C will have a phase set created with two versions: 0-180 (left-right) as well as 180-0 ...


68
Terence Chan: Multithreaded, mixed hardware description languages logic simulation on engineering workstations. Chi Ping Chang, Pacific Law Group, October 15, 2002: US06466898 (197 worldwide citation)

This invention describes a multithread HDL logic simulator that is unique from the prior arts. Specifically, it can process both VHDL and Verilog languages in a single program, and it uses special concurrent algorithms to accelerate the tool's performance on multiprocessor platforms to achieve ...


69
Alexander Andreev, Ivan Pavisic, Pedja Raspopovic: Metal layer assignment. LSI Logic Corporation, Mitchell Silberberg & Knupp, January 30, 2001: US06182272 (197 worldwide citation)

Routing layers are assigned to connection segments in integrated circuit design. A routing description that includes connection segments and a vertex where at least two of the connection segments connect to each other is obtained. A penalty is determined for the vertex based on a potential layer ass ...


70
Toshiya Kotani, Satoshi Tanaka, Koji Hashimoto, Soichi Inoue, Ichiro Mori: Method of setting process parameter and method of setting process parameter and/or design rule. Kabushiki Kaisha Toshiba, Finnegan Henderson Farabow Garrett & Dunner L, October 10, 2006: US07120882 (196 worldwide citation)

Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semicondu ...