41
Wise Adrian Philip, Robbins William Philip, Sotheran Martin William: Data pipeline system and data encoding method.. Pioneer Digital Design Centre, January 5, 1994: EP0576749-A1 (78 worldwide citation)

A pipeline structure processes data in a series of stages, each of which has a data input latch (LDIN) and passes it on to the next stage in the pipeline via a data output latch (LDOUT). The stages are preferably connected to two non-overlapping clock phases (PH0, PH1). Adjacent stages are also conn ...


42
So John Ling Wing: Integrated circuit. Texas Instruments, January 7, 1998: EP0817096-A2 (76 worldwide citation)

An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provide ...


43
Wester Aaron H: General-purpose array processor. Texas Instruments Incorporated, Levine Harold, Grossman Rene, Sadacca Stephen S, June 4, 1974: US3815095 (76 worldwide citation)

A general-purpose array processor allows each processor to transfer its output to any other processor in the array. Each processor contains its own memory, address register, and input selection multiplexer whereby an address may be transferred from a processor memory to its address register; and the ...


44
Hung Ta Huang: Dual socket upgradeable computer motherboard with automatic detection and enablement of inserted upgrade CPU chip. Acer Incorporated, David N Townsend and Townsend and Crew Slone, October 3, 1995: US05455927 (75 worldwide citation)

An upgradeable/downgradeable data processing system capable of operating with different types of central processing units (CPU). The system has a first socket for registration of a first CPU and a second socket for registration of a second CPU. Means are provided for preventing possible signal conte ...


45
William C Moyer, John Arends, Jeffrey W Scott: Method and apparatus for interfacing a processor to a coprocessor. Motorola, Susan C Hill, July 13, 1999: US05923893 (74 worldwide citation)

A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a b ...


46
Christopher M Hall, Gary D Phillips, William E Miller, David W Weinrich, Richard E Crippen, Robert M Salter III: In-system programming architecture for a multiple chip processor. National Semiconductor Corporation, Limbach & Limbach, October 15, 1996: US05566344 (74 worldwide citation)

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of regis ...


47
Christopher M Hall, Gary D Phillips, William E Miller, David W Weinrich, Robert M Salter III, Richard E Crippen: Non-volatile memory control and data loading architecture for multiple chip processor. National Semiconductor Corporation, Limbach & Limbach, April 22, 1997: US05623686 (71 worldwide citation)

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of regis ...


48
Christopher M Hall, Gary D Phillips, William E Miller, David W Weinrich, Robert M Salter III, Richard E Crippen: Multiple chip processor architecture with memory interface control register for in-system programming. National Semiconductor Corporation, Limbach & Limbach, December 3, 1996: US05581779 (69 worldwide citation)

An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of regis ...


49
Conterno Bruno, Gismondi Mauro, Luperini Vildo, Pesce Fernando: Multiprocessor system.. Finmeccanica, December 14, 1994: EP0628917-A2 (69 worldwide citation)

A multilevel multiprocessor system (1) comprising a number of processing units (3), each comprising a number of multiprocessor modules (5) connected to a first direct-access line (10) to form a first hierarchical level (region); the processing units (3) comprising subsets of multiprocessor modules ( ...


50
John Erik Lindholm, Stuart F Oberman: Execution of parallel groups of threads with per-instruction serialization. NVIDIA Corporation, Townsend and Townsend and Crew, December 15, 2009: US07634637 (68 worldwide citation)

In a processor, a SIMD group (a group of threads for which instructions are issued in parallel using single instruction, multiple data instruction issue techniques) is logically divided into two or more “SIMD subsets,” each containing one or more of the threads in the SIMD group. Each SIMD subset is ...