1
Private Ugochukwu Njoku
John R Flanagan, Daniel F Casper, Catherine C Huang, Matthew J Kalos, Ugochukwu C Njoku, Dale F Riedy, Gustav E Sittmann: Bi-directional data transfer within a single I/O operation. International Business Machines Corporation, Cantor Colburn, John Campbell, May 10, 2011: US07941570 (49 worldwide citation)

An article of manufacture, apparatus, and a method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit. The method includes the host computer system obtaining a transport command word (TCW) for an I/O operatio ...


2
Private Ugochukwu Njoku
John R Flanagan, Daniel F Casper, Catherine C Huang, Matthew J Kalos, Ugochukwu C Njoku, Dale F Riedy, Gustav E Sittmann: Bi-directional data transfer within a single I/O operation. International Business Machines Corporation, Cantor Colburn, John Campbell, July 23, 2013: US08495253 (11 worldwide citation)

An article of manufacture, apparatus, and a method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit. The method includes the host computer system obtaining a transport command word (TCW) for an I/O operatio ...


3
Mark S Miller, E Dean Tribble, Norman Hardy, Christopher T Hibbert: Diverse goods arbitration system and method for allocating resources in a distributed computer system. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, June 17, 1997: US05640569 (503 worldwide citation)

A diverse goods arbitration system and method allocates computer resources among bidding requesters. Bid slates are transmitted to an arbiter by users (requesters) requesting use of specified portions of the available computer resources. Each bid slate may contain a plurality of bids, each bid repre ...


4
Harold L McFarland, David R Stiles, Korbin S Van Dyke, Shrenik Mehta, John G Favor, Dale R Greenley, Robert A Cargnoni: Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags. Nexgen Microsystems, Townsend and Townsend Khourie and Crew, July 6, 1993: US05226126 (369 worldwide citation)

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report terminat ...


5
Keith Hogan, Thomas H Scholl, William E Witowsky: Real-time embedded software respository with attribute searching apparatus and method. Telogy Networks, Roberts & Brownell, July 7, 1998: US05778368 (303 worldwide citation)

The Real-Time Embedded Software Repository Apparatus fully characterizes, evaluates, and reuses real-time embedded software that is placed or stored in a repository database. The Repository System comprises at least one Repository Client and at least one Repository Server and utilizes simulation and ...


6
Laurence H Cooke, Christopher E Phillips, Dale Wong: Integrated processor and programmable data path chip for reconfigurable computing. Burns Doane Swecker & Mathis, October 19, 1999: US05970254 (250 worldwide citation)

A reconfigurable processor chip has a mixture of reconfigurable arithmetic cells and logic cells for higher effective utilization than a standard FPGA. The reconfigurable processor includes a standard microprocessor such as an embedded RISC processor. Many different types of interfaces are used to i ...


7
Kazuo Katsuki, Donald J Sauer, Danny Chin: Bus structure for multiprocessor system having separated processor section and control/memory section. Nippon Sheet Glass, Ratner & Prestia, December 3, 1996: US05581767 (187 worldwide citation)

The processor section comprises a matrix-line layout of processor units; each processor unit combined with adjacent processor units in row and column direction by means of IPC buses, which are two-way buses. The control/memory section comprises arrays of control/memory units corresponding one-to-one ...


8
Stephen M Trimberger: Method for compiling and executing programs for reprogrammable instruction set accelerator. Xilinx, Jeanette S Harms, Haynes & Davis Crosby Heafy Roach & May, May 12, 1998: US05752035 (183 worldwide citation)

A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a set of program instructions, to provide an ...


9
Jeff W Parrish, Farzin Maghoul, P Thyagarajan: Software project history database and method of operation. Taligent, Keith Stephens, September 3, 1996: US05553282 (180 worldwide citation)

A distributed program configuration database system is designed for use on a client-server network. The system consists of a plurality of program servers which maintain version information for various program components. A program developer, upon logging into a client terminal on the network, establ ...


10
Martin D Richek, Robert S Gready, Curtis R Jones Jr: Computer implemented method and apparatus for dynamic and automatic configuration of a computer system and circuit boards including computer resource allocation conflict resolution. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, October 26, 1993: US05257387 (164 worldwide citation)

A computerized system for dynamically and automatically configuring circuit boards to carry out functions from various manufacturers and a computer system without the user intervention. A single computer system may include, for example, a modem board, a video board, a disk controller board, and a mu ...