41
Edward A Lee, Jeffrey Bier: Multiprocessor system having statically determining resource allocation schedule at compile time and the using of static schedule with processor signals to control the execution time dynamically. The Regents of the University of California, Townsend and Townsend Khourie and Crew, November 22, 1994: US05367678 (108 worldwide citation)

A parallel processing architecture centralized controller for containing a granting access to a shared resource for a plurality of processors by use of a transaction schedule. The controller includes a memory for storing a schedule, a pointer into the memory for accessing a particular entry in the s ...


42
Michael S Cohen, K C Babu, R Balasubramanyam, Murali Ramanathan, P K Nanda Kumar: Scalable DSL access multiplexer with high reliability. E Cell Technologies, McDermott Will & Emery, November 5, 2002: US06477595 (107 worldwide citation)

A digital subscriber line (DSL) multiplexer is used in conjunction with a DSL modem to provide a reliable high speed connection for an end-user. The scaleable DSL multiplexer supports multiple DSL modems to a number of subscriber desiring increased bandwidth. The connection is reliably maintained by ...


43
Michael P Nolan: System for scheduling serial message transmission on a bus which is adoptable for rescheduling prioritized messages using a doubly-linked list. Motorola, Phillip H Melamed, January 23, 1990: US04896261 (105 worldwide citation)

A system (10) for scheduling serial message transmission on a single bus (11) having a plurality of messages to be sent stored in memory (21) with each message located between associated start and end message addresses (START, END). A message list or queue (28) of the messages to be sent is formed a ...


44
Kenneth J Hoguta, Amy J Rupert, Jesse Eugene Russell, Ronald Sherman: Method and apparatus for establishing a personalized connection with a network. AT&T, April 20, 2004: US06725303 (103 worldwide citation)

A method and apparatus for establishing a personalized connection with a network from a variety of different terminals and/or ports connected with the network. Subscribers to the network can be provided with a unique subscriber ID that may be used by the network to identify the subscriber. Furthermo ...


45
Mitsugu Satou, Shunichi Iwata: Computer system and semiconductor device on one chip including a memory and central processing unit for making interlock access to the memory. Mitsubishi Denki Kabushiki Kaisha, Burns Doane Swecker & Mathis, August 8, 2000: US06101584 (100 worldwide citation)

A central processing unit (CPU) having a built-in dynamic random-access memory (DRAM) with exclusive access to the DRAM when the CPU performs an interlock access to the DRAM. A memory controller prevents the DRAM from being externally accessed while the CPU is performing the interlock access. When t ...


46
Frederik Zandveld, Matthias Wendt, Marcel D Janssens: Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface. U S Philips Corporation, Debra K Stephens, August 19, 1997: US05659797 (100 worldwide citation)

A computer system includes a single-chip central processor (20) with handshaking and direct memory access (DMA) controllers for accommodating first and second types of DMA to a dynamic random access memory (DRAM) (34). The single-chip central processor (20) has a kernel processor (22) having cache, ...


47
Fong Lu, Cherng Yeuan, David H Doan: VL-bus/PCI-bus bridge. Opti, Fliesler Dubb Meyer & Lovejoy, August 4, 1998: US05790831 (97 worldwide citation)

A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV# to the VL-bus/system-bus bridge. If no other VL-bus device claims the cycle as well, then the VL-bus/PCI-bus bridge translates the cycle o ...


48
Cohen John B, Janson Paul E, McFarland Jr Harold L, Young Jr James B: Data processing system. Digital Equipment Corporation, January 9, 1973: US3710324 (97 worldwide citation)

A data processing system with improved data transfer capabilities. All units in the system, including a random access memory unit, are connected in parallel. Data is transferred between any two units asynchronously with respect to a processor unit which normally controls the system. Other units can ...


49
Jean Kodama, Borden T Moller, Paul R Nitza: Bus interface synchronization circuitry for reducing time between successive data transmission in a system using an asynchronous handshaking. Emulex Corporation, Spensley Horn Jubas & Lubitz, January 4, 1994: US05276807 (95 worldwide citation)

Bus interfacing circuitry provides for high speed communication of signals on a bus by using circuitry that synchronizes data transfers to a single reference point, executes commands from a dual-ranked buffer in order to reduce time consumed by external interrupts, and stores multiple bytes in a FIF ...


50
Paul Oliver Caffrey, John Alexander Petzen III, Dennis Brian King, Frank L Kerr III: Control systems and methods of providing the same. General Electric Company, Sutherland Asbill & Brennan, November 20, 2012: US08315718 (92 worldwide citation)

Control systems and methods for controlling certain systems, devices, and apparatus are described. A control system may include a memory and at least one processor. The memory may be operable to store both a Foundation Fieldbus protocol that facilitates communication with one or more Foundation Fiel ...