1
Lee R Reid, Tommy D Cody: Solid state multiprobe testing apparatus. Texas Instruments Incorporated, Carlton H Hoel, Robert O Groover, James T Comfort, April 29, 1986: US04585991 (176 worldwide citation)

A high density multiprobe including a multiprobe on a semiconductor substrate with contact pads selectively positioned in relation to the contacts of a device to be tested. Each of the selectively positioned contacts on the multiprobe semiconductor substrate include an elevated conductive surface th ...


2
David Cheng: Method and apparatus for handling wafers. David Cheng, Hickman & Beyer, December 26, 1995: US05479108 (146 worldwide citation)

A method and apparatus for handling wafers. A wafer pick moves along a horizontal x-axis to unload a wafer from a cassette and position the wafer over a chuck. The chuck moves upwardly along a z-axis perpendicular to the surface of the wafer and lifts the wafer off the pick. The pick retracts throug ...


3
Hugh W Littlebury, Marion I Simmons: Low resistance probe for semiconductor. Motorola, Joe E Barbee, January 5, 1993: US05177438 (142 worldwide citation)

A probe (10) that can be used for forming a low resistance electrical connection to a semiconductor die includes a contact (18) that is created on a compliant layer (12) which is supported by a substrate (11). Pressure applied to the contact (18) compresses the compliant layer (11) which causes a di ...


4
Glenn J Leedy: Flexible tester surface for testing integrated circuits. Skjerven Morrill MacPherson Franklin & Friel, February 19, 1991: US04994735 (138 worldwide citation)

The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silcon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side o ...


5
Jui Hsiang Liu, Dennis R Olsen: Probe card for testing unencapsulated semiconductor devices. U S Philips Corporation, Robert J Kraus, January 5, 1993: US05177439 (133 worldwide citation)

A probe card (8,18) for testing unencapsulated semiconductor devices (7,17) wherein the probe card (8,18) is made from a semiconductor material (10). A plurality of pyramidally shaped conductive protrusions or probe tips (11,41) project from the surface of the probe card (8,18) to mate with electrod ...


6
Satwinder Malhi, Oh K Kwon, Shivaling S Mahant Shetti: Flip-chip test socket adaptor and method. Texas Instruments Incorporated, W James Brady III, James T Comfort, Melvin Sharp, April 9, 1991: US05006792 (130 worldwide citation)

A test set socket adapter (20) comprises a substrate (28), a plurality of cantilever beams (32) and a package (30). A bare chip (22) may be inserted into and held by the test socket adapter (20) for insertion into a standard test socket. The cantilevers (32) are designed to deflect and compensate fo ...


7
Mark A Swart, Charles J Johnston, David R Van Loan: Test fixture alignment system for printed circuit boards. Everett Charles Technologies, Christie Parker & Hale, April 18, 1995: US05408189 (128 worldwide citation)

A test fixture for testing circuit boards includes an array of test probes mounted to a probe plate and held in contact with test points in circuits printed on the board. The circuit array is indexed with respect to a fiducial mark on the board. The fiducial mark is sensed, and an optical reading sh ...


8
Roger L Verkuil: Product wafer junction leakage measurement using corona and a kelvin probe. Pearne & Gordon, August 15, 2000: US06104206 (125 worldwide citation)

Corona charge is applied to a semiconductor product wafer to reverse bias PN junctions. Measurements of voltage decay in the dark and in the light are made and combined to determine a PN junction leakage characteristic. A portion of the dark measurement is taken in the light to permit normalizing th ...


9
Gregory G Boll, Harry J Boll: Integrated circuit probing apparatus including a capacitor bypass structure. G G B, Irwin Ostroff, Erwin W Pfeifle, December 13, 1994: US05373231 (124 worldwide citation)

A device for testing the performance of high speed integrated circuits (ICs) while in wafer form or separated from the wafer which includes first and second spaced-apart probes fixedly mounted on a support member for accurately positioning the first and second probes in three dimensions for contacti ...


10
Glenn J Leedy: Test device for testing integrated circuits. Skjerven Morrill MacPherson Franklin & Friel, July 23, 1991: US05034685 (124 worldwide citation)

Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By CAD, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and pat ...