1
Zahir Ebrahim: System and method for preserving message order while employing both programmed I/O and DMA operations. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, March 23, 1999: US05887134 (672 worldwide citation)

In a cluster of computer nodes, each node has network interface and at least one processor. Transmission of a multipart message from a first node to a second node is initiated by sending to a network interface of the first node a sequence of PIO store and DMA store commands, each PIO store and DMA s ...


2
Zahir Ebrahim: Method and apparatus for implementing hardware protection domains in a system with no memory management unit (MMU). Sun Microsystems, Ken J Koestner, Skjerven Morrill MacPherson Franklin & Friel, November 16, 1999: US05987557 (185 worldwide citation)

A low overhead, efficient, and simple protection check circuit is inserted into a data path between a master requester and a target resource such as a memory or input/output device. The master requester initiates a memory request, a pio access request, or a dma transaction directed to the target res ...


3
Zahir Ebrahim: System for context-dependent name resolution. Sun Microsystems, B Noel Kivlin, Conley Rose & Tayon PC, November 28, 2000: US06154777 (168 worldwide citation)

A context-dependent, multiply binding name resolution system. A name resolver is provided, connected to either a requester's system or a receiver's system, or both. Requests to a given service or domain name are resolved to the appropriate IP address. The intended recipient of the request is resolve ...


4
Zahir Ebrahim, Satyanarayana Nishtala, William C Van Loo, Kevin Normoyle, Paul Loewenstein, Louis F Coffin III: Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system. Sun Microsystems, Steven F Caserza, Flehr Hohbach Test Albritton & Herbert, May 18, 1999: US05905998 (81 worldwide citation)

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one ...


5
Zahir Ebrahim, Kevin Normoyle, Satyanarayana Nishtala, William C Van Loo: Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, July 1, 1997: US05644753 (80 worldwide citation)

A multiprocessor computer system has data processors and a main memory coupled to a system controller. Each data processor has a cache memory. Each cache memory has a cache controller with two ports for receiving access requests. A first port receives access requests from the associated data process ...


6
Satyanarayana Nishtala, Zahir Ebrahim, William C Van Loo, Kevin Normoyle, Leslie Kohn, Louis F Coffin III: Packet switched cache coherent multiprocessor system. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, May 27, 1997: US05634068 (77 worldwide citation)

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. All of the sub-systems inclu ...


7
Zahir Ebrahim, Satyanarayana Nishtala, William C Van Loo, Kevin Normoyle, Paul Loewenstein, Louis F Coffin III: Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, August 5, 1997: US05655100 (76 worldwide citation)

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one ...


8
Zahir Ebrahim: Power sequence controller with wakeup logic for enabling a wakeup interrupt handler procedure. Sun Microsystems, Gary S Flehr Hohbah Test Albritton & Herbert Williams, March 2, 1999: US05878264 (72 worldwide citation)

A power sequence controller contains wakeup logic for responding to each wakeup event signal intercepted by the power sequence controller. The wakeup logic compares the intercepted wakeup event signal with a wakeup filter mask to determine if the wakeup event signal should be processed or ignored. I ...


9
Charles E Narad, Zahir Ebrahim, Satyanarayana Nishtala, William C Van Loo, Kevin B Normoyle, Louis F Coffin III, Leslie Kohn: Method and apparatus for reducing power consumption in a computer network without sacrificing performance. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, November 25, 1997: US05692197 (69 worldwide citation)

A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independentl ...


10
Satyanarayana Nishtala, Zahir Ebrahim, William C Van Loo, Paul Loewenstein, Sue K Lee, Louis F Coffin III: Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system. Sun Microsystems, Test Albritton & Herbert Flehr Hohbach, December 3, 1996: US05581729 (67 worldwide citation)

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two ...