1
Mitsuhiro Noguchi, Akira Goda, Yuji Takeuchi: Data writing method for semiconductor memory device and semiconductor memory device. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, March 22, 2005: US06870773 (81 worldwide citation)

A semiconductor memory device includes a first memory cell block capable of rewriting data and having at least one first memory cell, and a second memory cell block capable of rewriting data and having at least one second memory cell adjoining the first memory cell. A data writing method for the sem ...


2
Hiroshi Watanabe, Kazuhiro Shimizu, Yuji Takeuchi, Seiichi Aritome: Nonvolatile semiconductor memory device. Kabushiki Kaisha Toshiba, Banner & Witcoff, March 30, 1999: US05889304 (78 worldwide citation)

Disclosed is the memory cell of an EEPROM having a p-type silicon substrate and a floating gate formed on this silicon substrate via a tunnel oxide film. The element region set in the silicon substrate projects from the surface of a trench-type element isolation region. The projecting element region ...


3
Masayuki Ichige, Koji Hashimoto, Tatsuaki Kuji, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Koji Sakui: Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, January 18, 2005: US06845042 (76 worldwide citation)

A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction an ...


4
Hiroshi Watanabe, Hiroshi Nakamura, Kazuhiro Shimizu, Seiichi Aritome, Toshitake Yaegashi, Yuji Takeuchi, Kenichi Imamiya, Ken Takeuchi, Hideko Oodaira: Nonvolatile semiconductor memory. Kabushiki Kaisha Toshiba, Banner & Witcoff, March 5, 2002: US06353242 (69 worldwide citation)

A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has a plurality of contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. ...


5
Mitsuhiro Noguchi, Akira Goda, Yuji Takeuchi: Data writing method for semiconductor memory device and semiconductor memory device. Kabushiki Kaisha Toshiba, Oblon Spivak McCelland Maier & Neustadt P C, October 25, 2005: US06958938 (65 worldwide citation)

A data writing method for a semiconductor memory device includes writing data into the first memory cell, rewriting the data into the first memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one first ref ...


6
Kazuhiro Shimizu, Yuji Takeuchi: Non-volatile semiconductor memory device and manufacturing method thereof. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, April 29, 2003: US06555427 (64 worldwide citation)

A non-volatile semiconductor memory device with a small variation in capacitance-coupling to the stacked gate for memory miniaturization. The device has a memory cell array in which memory cells are arranged in array. Each cell has a first gate and a second gate on a semiconductor substrate. The fir ...


7
Kazuhiro Shimizu, Hiroshi Watanabe, Yuji Takeuchi, Seiichi Aritome, Toshiharu Watanabe: Semiconductor memory device having a first source line arranged between a memory cell string and bit lines in the direction crossing the bit lines and a second source line arranged in parallel to the bit lines. Kabushiki Kaisha Toshiba, Banner & Witcoff, December 12, 2000: US06160297 (58 worldwide citation)

A semiconductor device comprises select gates and control gates of a plurality of memory cells therebetween so that gate members on upper portions of stacked gates may cross element regions. A metal interconnection is disposed parallel to an upper layer of the element region. A source line SL is arr ...


8
Yuji Takeuchi, Masayuki Ichige, Akira Goda: Semiconductor device. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, April 13, 2004: US06720612 (43 worldwide citation)

A NAND type semiconductor device is disclosed, in which a first insulating film embedded between the memory cell gates and between the memory cell gates and the selecting gate does not contain nitrogen as a major component, a second insulating film is formed on the first insulating film, and an inte ...


9
Hiroshi Watanabe, Yuji Takeuchi, Kazuhiro Shimizu, Seiichi Aritome: Semiconductor memory device having shallow trench isolation structure. Kabushiki Kaisha Toshiba, Loeb & Loeb, May 2, 2000: US06057580 (37 worldwide citation)

In a nonvolatile semiconductor memory device, those sides of the gate insulating film and the floating gate electrode which oppose an inner side of a trench are oxidized to form an oxide film. The gate insulating film, the floating gate electrode, and that portion of semiconductor substrate which is ...


10
Kazuhiro Shimizu, Yuji Takeuchi: Non-volatile semiconductor memory device and manufacturing method thereof. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, November 16, 2004: US06818508 (37 worldwide citation)

A method of manufacturing a non-volatile semiconductor memory device, including forming a first gate insulating film, on a semiconductor substrate; forming a first conductive layer as the lowest layer of a charge-storage layer on the first gate insulating film; forming a masking material on the firs ...