1
Hirotsugu Kojima, Atsushi Kiuchi, Yuichi Takitsune, Katsumi Yamamoto: Wireless communication system and microcomputer. Renesas Technology Corporation, Mattingly Stanger Malur & Brundidge P C, May 1, 2007: US07212786 (11 worldwide citation)

Providing a wireless communication device that, even if clock stop of a radio frequency part is controlled by a baseband part operating on the same clock signal, can resume clock oscillation, and makes it easy to time the clock reactivation to other operations based on a shared clock. The wireless c ...


2
Yasuyuki Murakami, Shigezumi Matsui, Kunihiko Nishiyama, Atsushi Kiuchi, Yuichi Takitsune: Data processer and data processing system. Hitachi, Hitachi ULSI Systems, Miles & Stockbridge P C, April 1, 2003: US06542982 (6 worldwide citation)

In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of ...


3
Yasuyuki Murakami, Shigezumi Matsui, Kunihiko Nishiyama, Atsushi Kiuchi, Yuichi Takitsune: Cell phones with instruction pre-fetch buffers allocated to low bit address ranges and having validating flags. Hitachi, Hitachi ULSI Systems, Miles & Stockbridge P C, August 13, 2002: US06434691 (5 worldwide citation)

In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of ...


4
Yasuyuki Murakami, Shigezumi Matsui, Kunihiko Nishiyama, Atsushi Kiuchi, Yuichi Takitsune: Data processor and data processing system. Mitchell W Shapiro, Miles & Stockbridge PC, August 30, 2001: US20010018735-A1

In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of ...


5
Hirotsugu Kojima, Atsushi Kiuchi, Yuichi Takitsune, Katsumi Yamamoto: Wireless communication system and microcomputer. Mattingly Stanger & Malur PC, October 14, 2004: US20040203389-A1

Providing a wireless communication device that, even if clock stop of a radio frequency part is controlled by a baseband part operating on the same clock signal, can resume clock oscillation, and makes it easy to time the clock reactivation to other operations based on a shared clock. The wireless c ...


6
Yasuyuki Murakami, Shigezumi Matsui, Kunihiko Nishiyama, Atsushi Kiuchi, Yuichi Takitsune: Data processer and data processing system. Vorys Sater Seymour Pease, August 29, 2002: US20020120829-A1

In order to simplify the instruction prefetch architecture for use with the programs having few loops, and having instructions almost in linear and sequential addresses, the bus controller in accordance with the present invention for controlling the bus in an external memory includes a plurality of ...



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