1
Wei Chen, Devendra Kumar Sadana, Yuan Taur: SOI CMOS structure. International Business Machines Corporation, Robert M Trepp, June 16, 1998: US05767549 (202 worldwide citation)

An integrated circuit is described incorporating a substrate, a layer of insulator, a layer of silicon having raised mesas and thin regions therebetween to provide ohmic conduction between mesas, electronic devices on the mesas, and interconnection wiring. The invention overcomes the problem of a fl ...


2
Heemyong Park, Yuan Taur, Hsing Jen C Wann: Forming steep lateral doping distribution at source/drain junctions. International Business Machines Corporation, Joseph P Abate, Connolly Bove Lodge & Hutz, July 31, 2001: US06268640 (105 worldwide citation)

A semiconductor device is fabricated by implanting into a semiconductor substrate non-doping ions at a tilt angle of at least about 10° to laterally extend preamorphization of the substrate portion and then implanting into the substrate dopants for providing source/drain extensions or halo doping or ...


3
Kevin K Chan, Guy M Cohen, Yuan Taur, Hon Sum P Wong: Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques. International Business Machines Corporation, Marian Underweiser Esq, McGinn & Gibb PLLC, April 2, 2002: US06365465 (75 worldwide citation)

A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the lamina ...


4
Burn J Lin, Yuan Taur: System for real-time monitoring the characteristics, variations and alignment errors of lithography structures. International Business Machines Corporation, John J Goodwin, April 29, 1986: US04585342 (46 worldwide citation)

A system for evaluating and measuring the performance of lithographic structures, and more particularly for monitoring the optical parameters of a projection lithography system which uses the instant electrical readout from an array of photosensitive detectors fabricated on a silicon wafer in combin ...


5
Barbara A Chappell, Bijan Davari, George A Sai Halasz, Yuan Taur: SRAM cell with capacitor. International Business Machines Corporation, David Aker, July 30, 1996: US05541427 (36 worldwide citation)

A storage latch comprising a gate insulating layer over the substrate, shallow trenches formed through the insulating layer and in the substrate to provide device insulation; and doped regions in the substrate between the shallow trenches. The doped regions define sources and drains. Gate stacks are ...


6
Yuan Taur, Hon Sum Philip Wong: Method for fabricating a self-aligned double-gate MOSFET by selective lateral epitaxy. International Business Machines Corporation, Robert P Tassinari Jr, July 8, 1997: US05646058 (35 worldwide citation)

A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial films are then replaced by a gate material (e.g ...


7
Jack Oon Chu, Louis Lu Chen Hsu, Jack Allan Mandelman, Yuan Chen Sun, Yuan Taur: Vertical double-gate field effect transistor. International Business Machines Corporation, Susan M Murray, November 18, 1997: US05689127 (29 worldwide citation)

A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. ...


8
Ghavam G Shahidi, Denny D Tang, Yuan Taur: SOI lateral bipolar transistor with edge-strapped base contact and method of fabricating same. International Business Machines, Scully Scott Murphy & Presser, March 29, 1994: US05298786 (28 worldwide citation)

A silicon-on-insulator lateral bipolar transistor having an edge-strapped base contact is disclosed. A thin layer of oxide is deposited on a silicon-on-insulator structure and a layer of polysilicon is deposited on the thin oxide layer that is patterned and etched to form an extrinsic base region of ...


9
Yuan Taur, Hon Sum P Wong: Self-aligned double-gate MOSFET by selective lateral epitaxy. International Business Machines Corporation, Robert P Tassinari Jr, February 18, 1997: US05604368 (21 worldwide citation)

A novel method of fabricating a double-gate MOSFET structure is disclosed. The method utilizes selective lateral epitaxial growth of silicon into a thin gap formed between two sacrificial dielectric films for accurate thickness control. The sacrificial films are then replaced by a gate material (e.g ...


10
Jack Oon Chu, Louis Lu Chen Hsu, Jack Allan Mandelman, Yuan Chen Sun, Yuan Taur: Vertical double-gate field effect transistor. International Business Machines Corporation, Joseph P Abate, Susan Murray, July 14, 1998: US05780327 (18 worldwide citation)

A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. ...