1
Yuan C Chou: Method of read-set and write-set management by distinguishing between shared and non-shared memory regions. Oracle America, Osha • Liang, June 26, 2012: US08209499 (42 worldwide citation)

A method of read-set and write-set management distinguishes between shared and non-shared memory regions. A shared memory region, used by a transactional memory application, which may be shared by one or more concurrent transactions is identified. A non-shared memory region, used by the transactiona ...


2
Santosh G Abraham, Yuan C Chou: Method and apparatus for dynamically allocating registers in a windowed architecture. Sun Microsystems, Park Vaughan & Fleming, Edward J Grundler, October 24, 2006: US07127592 (39 worldwide citation)

One embodiment of the present invention provides a system that dynamically allocates physical registers in a windowed processor architecture. The system includes a physical register file and a register map that maps architectural registers defined within an executing program to physical registers wi ...


3
Yuan C Chou: Method and apparatus for selectively executing different executable code versions which are optimized in different ways. Sun Microsystems, Park Vaughan & Fleming, June 2, 2009: US07543282 (22 worldwide citation)

One embodiment of the present invention provides a system that selectively executes different versions of executable code for the same source code. During operation, the system first receives an executable code module which includes two or more versions of executable code for the same source code, w ...


4
Yuan C Chou, Santosh G Abraham: Method and apparatus for performing register file checkpointing to support speculative execution within a processor. Sun Microsystems, Park Vaughan & Fleming, January 6, 2009: US07475230 (13 worldwide citation)

One embodiment of the present invention provides a system that performs register file checkpointing to support speculative execution within a processor. During operation, the system commences speculative execution of a program from a point of speculation, at which the outcome of a long latency instr ...


5
Sorin Iacobovici, Sudarshan Kadambi, Yuan C Chou: Multi-stride prefetcher with a recurring prefetch table. Sun Microsystems, Gunnison McKay & Hodgson L, Forrest Gunnison, February 3, 2009: US07487296 (12 worldwide citation)

A multi-stride prefetcher includes a recurring prefetch table that in turn includes a stream table and an index table. The stream table includes a valid field and a tag field. The stream table also includes a thread number field to help support multi-threaded processor cores. The tag field stores a ...


6
Yuan C Chou: Method and system for efficient implementation of very large store buffer. Sun Microsystems, Martine Penilla & Gencarella, October 6, 2009: US07600098 (12 worldwide citation)

A method and system for efficient implementation of a large store buffer within a processor includes a store buffer within a processor having a first component configured to hold a plurality of younger stores requested by the processor and a second component configured to hold a plurality of older s ...


7
Yuan C Chou, Eric W Mahurin: Reducing power consumption and resource utilization during miss lookahead. Oracle International Corporation, Park Vaughan Fleming & Dowler, April 14, 2015: US09009449 (9 worldwide citation)

A system that executes program instructions on a processor is described. During a normal-execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system speculatively executes subsequent ins ...


8
Yuan C Chou, Yasuko Watanabe: Accuracy of correlation prefetching via block correlation and adaptive prefetch degree selection. Oracle America, Park Vaughan Fleming & Dowler, April 12, 2011: US07925865 (7 worldwide citation)

In the described embodiments, a method for prefetching data and/or instructions may include generating control flow information for each retired branch instruction. A correlation table may be maintained based on the generated control flow information and cache miss addresses for each retired instruc ...


9
Yuan C Chou: Structure and method for achieving very large lookahead instruction window via non-sequential instruction fetch and issue. Sun Microsystems, Gunnison McKay & Hodgson L, Forrest Gunnison, January 19, 2010: US07650485 (6 worldwide citation)

A multithreading processor achieves a very large lookahead instruction window by allowing non-sequential fetch and processing of the dynamic instruction stream. A speculative thread is spawned at a specified point in the dynamic instruction stream and the instructions subsequent to the specified poi ...


10
Lawrence A Spracklen, Yuan C Chou, Santosh G Abraham: Efficient caching of stores in scalable chip multi-threaded systems. Oracle America, Gunnison McKay & Hodgson L, Philip McKay, September 7, 2010: US07793044 (6 worldwide citation)

In accordance with one embodiment, an enhanced chip multiprocessor permits an L1 cache to request ownership of a data line from a shared L2 cache. A determination is made whether to deny or grant the request for ownership based on the sharing of the data line. In one embodiment, the sharing of the d ...