1
Yu Hao Yang: Split gate flash memory with minimum over-erase problem. Windbond Electronics, W Wayne Liauh, July 25, 2000: US06093945 (44 worldwide citation)

A split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an inter-poly dielectric layer. The split-gate flash memory is formed by (a) forming a first dielectric layer having a trench region on a substrate ...


2
Yu Hao Yang: Fabrication method for increasing the coupling efficiency of ETOX flash memory devices. Winbond Electronics Corporation, Finnegan Henderson Farabow Garrett & Dunner L, November 28, 2000: US06153904 (16 worldwide citation)

A method of manufacturing an electron tunnel oxide (ETOX) flash memory device having an improved coupling efficiency includes sequentially forming a tunnel oxide, a floating gate, a dielectric layer, and a control gate on a substrate, where the tunnel oxide and the bottom of the floating gate are fo ...


3
Yu Hao Yang: Method for making split gate flash memory cells with high coupling efficiency. Winbond Electronics, W Wayne Liauh, December 11, 2001: US06329248 (12 worldwide citation)

A process for making split-gate semiconductor flash memory contains an outwardly-diverging control gate stacked on but separated from a pair of opposing floating gates via an interpoly dielectric layer. This process includes the steps of: (a) forming a first dielectric layer having a trench region o ...


4
Yu Hao Yang: Structure of a non-destructive readout dynamic random access memory. Winbond Electronics, Thomas Kayden Horstemeyer & Risley, March 21, 2000: US06040595 (3 worldwide citation)

A structure of dynamic random access memory includes a field effect transistor (FET), a capacitor, a world line and a bit line. The gate of the FET is electrically coupled to the word line in which a voltage source is supplied through the world line to the gate. The drain region of the FET is electr ...


5
Yu Hao Yang: Deep submicron MOS transistors with a self-aligned gate electrode. Windbond Electronics, W Wayne Liauh, December 5, 2000: US06155537 (3 worldwide citation)

A MOS transistor with a pair of lightly doped drain (LDD) sub-regions in the substrate and whose gate electrode is self-aligned with a non-doped gate oxide layer overlying the channel region between the two LDD sub-regions. The MOS transistor is characterized as having the following structure: (a) a ...


6
Kuei Chang Liang, Yu Hao Yang: Method of forming local interconnection of a static random access memory. Winbond Electronics, Finnegan Henderson Farabow Garrett & Dunner L, November 9, 1999: US05979784 (2 worldwide citation)

A method of forming local interconnection of a SRAM, including the following steps: First, an NMOS and a PMOS are formed on a P-well and an N-well on a substrate, respectively. An isolation oxide layer is formed and the isolation oxide layer on a node is removed. A thin polysilicon layer is formed a ...


7
Yu Hao Yang: Method for forming a MOS structure having sidewall source/drain and embedded gate. Winbond Electronics Corporation, Proskauer Rose, March 14, 2000: US06037231 (1 worldwide citation)

A MOS device is provided with a reduced source and drain area. This is accomplished by first providing a MOS device with a buried gate region. The buried gate region is located on top of a channel region, which runs horizontally along the bottom of the gate trench. The source and drain regions are a ...


8
Yu Hao Yang: Method for forming a dielectric layer of a semiconductor. Birch Stewart Kolasch & Birch, December 16, 2004: US20040253837-A1

A method for forming a dielectric layer of a semiconductor is described. At first, providing a substrate with a metal-conductive layer having been formed thereon. Next covering the substrate with a membrane having a plurality of micro-holes. Afterward spraying a fluid dielectric on the membrane havi ...