1
Kevin L Denis, Yu Chen, Paul S Drzaic, Joseph M Jacobson, Peter T Kazlas: Process for fabricating thin film transistors. E Ink Corporation, David J Cole, November 30, 2004: US06825068 (201 worldwide citation)

Transistors are formed by depositing at least one layer of semiconductor material on a substrate comprising a polyphenylene polyimide. The substrate permits the use of processing temperatures in excess of 300° C. during the processes used to form the transistors, thus allowing the formation of high ...


2
Yee Chia Yeo, How Yu Chen, Chien Chao Huang, Wen Chin Lee, Fu Liang Yang, Chenming Hu: Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors. Taiwan Semiconductor Manufacturing Company, Slater & Matsil L, March 15, 2005: US06867433 (172 worldwide citation)

In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the ...


3
Paul S Drzaic, Karl R Amundson, Gregg M Duthaler, Peter T Kazlas, Yu Chen: Minimally-patterned semiconductor devices for display applications. E Ink Corporation, David J Cole, April 18, 2006: US07030412 (156 worldwide citation)

A thin-film transistor array comprises at least first and second transistors. Each transistor comprises a source electrode, a drain electrode a semiconductor electrode, a gate electrode, and a semiconductor layer. The semiconductor layer is continuous between the first and second transistors. The se ...


4
Karl R Amundson, Yu Chen, Kevin L Denis, Paul S Drzaic, Peter T Kazlas, Andrew P Ritenour: Backplanes for display applications, and components for use therein. E Ink Corporation, David J Cole, October 3, 2006: US07116318 (156 worldwide citation)

A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is dispos ...


5
Yu Chen Shen, Mira S Misra: Indium gallium nitride separate confinement heterostructure light emitting devices. Lumileds Lighting U S, Rachel V Leiterman, Patent Law Group, December 21, 2004: US06833564 (128 worldwide citation)

A III-nitride light emitting device including a substrate, a first conductivity type layer overlying the substrate, a spacer layer overlying the first conductivity type layer, an active region overlying the spacer layer, a cap layer overlying the active region, and a second conductivity type layer o ...


6
Kuo Nan Yang, Yi Ling Chan, You Lin Chu, Hou Yu Chen, Fu Liang Yang, Chenming Hu: High performance PD SOI tunneling-biased MOSFET. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, February 11, 2003: US06518105 (124 worldwide citation)

A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made somewhat longer than normal and a region near ...


7
Ranganathan Nagarajan, Chirayarikathuveedu Sankarapillai Premachandran, Yu Chen, Vaidyanathan Kripesh: Wafer-level package for micro-electro-mechanical systems. Institute of Microelectronics, Nath & Associates PLLC, Harold L Novick, Marvin C Berkowitz, January 25, 2005: US06846725 (122 worldwide citation)

A method for forming wafers having through-wafer vias for wafer-level packaging of devices, the method comprising the steps of depositing metal on one of two wafers; bonding the two wafers using the metal deposited on the one of the two wafers; forming a through-wafer via in one of the two wafers; f ...


8
Kun Tsan Wu, Yu Chen Chen, Chien Cheng Chen: IC card connector. Hon Hai Precision, Wei Te Chung, August 28, 2001: US06280254 (115 worldwide citation)

An IC card connector comprises an insulative housing and a plurality of contacts. A plurality of passageways is defined through the insulative housing for receiving the corresponding contacts therein. Each contact comprises a first contacting arm, a second contacting arm and a retaining portion conn ...


9
David Yu Chen: Power conservation in synchronous SRAM cache memory blocks of a computer system. United Microelectronics Corporation, Cushman Darby & Cushman IP Group of Pillsbury Madison & Sutro, May 12, 1998: US05752045 (103 worldwide citation)

A synchronous cache memory power conservation apparatus for conserving power of the cache SRAM memory blocks in cached computer systems. The power conservation apparatus is included as a portion of the logic of the cache controller of the computer system. The power conservation apparatus monitors th ...


10
Hao Yu Chen, Yee Chia Yeo, Fu Liang Yang, Chenming Hu: Semiconductor nano-rod devices. Taiwan Semiconductor Manufacturing Company, Slater & Matsil L, February 15, 2005: US06855606 (97 worldwide citation)

In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by an ...



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