1
Akira Kabemoto, Naohiro Shibata, Toshiyuki Muta, Takayuki Shimamura, Hirohide Sugahara, Junji Nishioka, Takatsugu Sasaki, Satoshi Shinohara, Yozo Nakayama, Jun Sakurai, Hiroaki Ishihata, Takeshi Horie, Toshiyuki Shimizu: Coherence apparatus for cache of multiprocessor. Fujitsu, PFU, Staas & Halsey, March 30, 1999: US05890217 (61 worldwide citation)

A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using t ...


2
Yozo Nakayama, Masahito Kubo, Yuuichi Yawata: Condition code producing system. Panafacom, Staas & Halsey, November 29, 1988: US04788655 (37 worldwide citation)

A condition code producing system for an arithmetic unit which is controlled by a micro program and operate on binary floating point data produces a condition code having a plurality of bits and describing an attribute of the binary floating point data. The condition code producing system comprises: ...


3
Takatsugu Sasaki, Akira Kabemoto, Hirohide Sugahara, Junji Nishioka, Yozo Nakayama, Jun Sakurai, Toshiyuki Muta, Takayuki Shimamura: Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system. Fujitsu, PFU, Armstrong Westerman Hattori McLeland & Naugthon, July 18, 2000: US06092173 (21 worldwide citation)

A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control un ...


4
Haruhiko Ueno, Yozo Nakayama: Interruption handling system. Fujitsu, Staas & Halsey, April 5, 1994: US05301331 (13 worldwide citation)

An interruption processing system enables a basic CPU resource using process to be executed asynchronously, enabling an interruption handler to be easily created. Interruption handling of the basic CPU resource using process interruption handler to be executed asynchronously enables corresponding in ...


5
Takatsugu Sasaki, Akira Kabemoto, Hirohide Sugahara, Junji Nishioka, Satoshi Shinohara, Yozo Nakayama, Jun Sakurai, Naohiro Shibata, Toshiyuki Muta, Takayuki Shimamura: Multiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer system. Fujitsu, PFU, Armstrong Westerman Hattori McLeland & Naughton, March 14, 2000: US06038674 (8 worldwide citation)

A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control un ...


6
Rajarshi Mukherjee, Toshiya Mima, Yozo Nakayama: Method and system for design verification and debugging of a complex computing system. Fujitsu, Baker Botts L, June 3, 2008: US07383168 (4 worldwide citation)

A method and system for element testing is described. A first module is generated and has at least one associated state. A second module is generated based on the first module. The second module is associated with a test element. The test element is controlled based on the second module and the stat ...


7
Rajarshi Mukherjee, Toshiya Mima, Yozo Nakayama: Method and system for design verification. Baker Botts, July 8, 2004: US20040133409-A1

A method and system for element testing is described. A first module is generated and has at least one associated state. A second module is generated based on the first module. The second module is associated with a test element. The test element is controlled based on the second module and the stat ...