1
Yowjuang W Liu, Donald L Wollesen: Trench-gated vertical combination JFET and MOSFET devices. Advanced Micro Devices, Foley & Lardner, December 19, 2000: US06163052 (121 worldwide citation)

A combination vertical MOSFET and JFET device (18,22) is formed in a mesa (20,24) of semiconductor material. A top gate (44,68) of the device is formed by creating a preferably annular trench (36,58) that extends downwardly from the surface of the semiconductor layer, creating a thin gate insulator ...


2
Yowjuang W Liu, Kuang Yeh Chang: Method for forming advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits. Advanced Micro Devices, Townsend and Townsend and Crew, March 2, 1999: US05877049 (117 worldwide citation)

A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without ...


3
Yowjuang W Liu, Kuang Yeh Chang: Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits. Advanced Micro Devices, Townsend and Townsend and Crew, March 4, 1997: US05608253 (111 worldwide citation)

A novel MOS transistor structure for improving device scaling by improving short channel control includes a buried back gate beneath a channel region of the MOS transistor. A separate contact to a well that is electrically communicated to the buried back gate improves short channel controls without ...


4
Yowjuang W Liu, Kuang Yeh Chang: Reverse damascene via structures. Advanced Micro Devices, Lowe Price LeBlanc & Becker, December 2, 1997: US05693568 (60 worldwide citation)

A reliable interconnection pattern is formed by depositing first and second conductive layers, etching to form a conductive pattern in the first conductive layer and etching to form an interconnection comprising a portion of the second conductive layer. Advantageously, the need to form openings in d ...


5
Yowjuang W Liu, Feng Qian, Tze Kwai Kelvin Lai: Method of making semiconductor device with self-aligned insulator. Advanced Micro Devices, Lowe Price LeBlanc & Becker, January 27, 1998: US05712173 (31 worldwide citation)

A semiconductor device having the advantages of an SOI structure without the attendant disadvantages is obtained by implanting oxygen ions using the gate electrode as a mask, and heating to form thin, self-aligned buried oxide regions extending from a field oxide region under source/drain regions se ...


6
James J Hsu, Yowjuang W Liu: Process for producing optimum intrinsic, long channel, and short channel MOS devices in VLSI structures. Advanced Micro Devices, John P Taylor, February 25, 1992: US05091324 (31 worldwide citation)

Highly doped short channel NMOS devices with punch-through protection; intrinsic NMOS devices with low threshold voltage; and long channel NMOS and PMOS devices with low body factor; are constructed by providing one or more lightly doped P regions in a semiconductor wafer in which intrinsic and long ...


7
Yu Sun, Yowjuang W Liu: Post-gate LOCOS. Advanced Micro Devices, Foley & Lardner, March 18, 1997: US05612249 (31 worldwide citation)

A method of defining a local oxidation of silicon (LOCOS) field isolation process after a poly gate is deposited. A gate oxide is grown on a silicon substrate, and then poly or amorphous silicon is deposited. A thin layer of PECVD or LPCVD oxide is deposited on the poly, and LPCVD nitride is then de ...


8
Yowjuang W Liu, Ming Ren Lin: High quality isolation for high density and high performance integrated circuits. Advanced Micro Devices, Townsend and Townsend and Crew, October 26, 1999: US05972773 (29 worldwide citation)

A novel semiconductor fabrication process having the advantages of conventional LOCOS (process simplicity and reduced defects) while providing a scaleable, planar isolation region between active regions formed in a semiconductor substrate. The preferred process includes formation of a barrier layer ...


9
Yowjuang W Liu, Donald L Wollesen: Fully recessed semiconductor device and method for low power applications with single wrap around buried drain region. Advanced Micro Devices, Fenwick & West, November 14, 2000: US06147378 (27 worldwide citation)

A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region ...


10
Yowjuang W Liu, Kuang yeh Chang: Reverse CMOS method for dual isolation semiconductor device. Advanced Micro Devices, February 23, 1999: US05874328 (26 worldwide citation)

CMOS transistors are formed by a damascene process resulting in field oxide regions exhibiting essentially no bird's beak portions. A trench isolation is also formed in a source/drain region each transistor between adjacent junctions.