1
Eb Eshun
Shashank S Ekbote, Kwan Yong Lim, Ebenezer Eshun, Youn Sung Choi: Silicide formation due to improved SiGe faceting. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, July 28, 2015: US09093298 (5 worldwide citation)

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is e ...


2
Eb Eshun
Shashank S Ekbote, Kwan Yong Lim, Ebenezer Eshun, Youn Sung Choi: Silicide formation due to improved SiGe faceting. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, December 1, 2015: US09202883 (1 worldwide citation)

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is e ...


3
Eb Eshun
Shashank S Ekbote, Kwan Yong Lim, Ebenezer Eshun, Youn Sung Choi: Silicide formation due to improved SiGe faceting. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, August 2, 2016: US09406769

An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is e ...


4
Youn Sung Choi, Greg Charles Baldwin: Method for improving device performance using dual stress liner boundary. Texas Instruments Incorporated, Jacqueline J Garner, Frederick J Telecky Jr, October 14, 2014: US08859357 (6 worldwide citation)

An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside ...


5
Ryoung han Kim, Youn Sung Choi: Method of printing multiple structure widths using spacer double patterning. Texas Instruments Incorporated, Jacqueline J Garner, Frank Cimino, May 12, 2015: US09029263 (4 worldwide citation)

An integrated circuit containing linear structures on regular pitch distances may be formed by forming linear mandrels over a layer of material for the linear structures, with mandrel pitch distances that are twice the desired linear structures' pitch distances. Mandrels for a first plurality of lin ...


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Youn Sung Choi, Greg Charles Baldwin: Integrated circuit with dual stress liner boundary. TEXAS INSTRUMENTS INCORPORATED, Tunelap Daniel Chan, Frank D Cimino, January 10, 2017: US09543437 (1 worldwide citation)

An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily insid ...


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Youn Sung Choi, Greg Charles Baldwin: Method for improving device performance using dual stress liner boundary. TEXAS INSTRUMENTS INCORPORATED, Tuenlap D Chan, Frank D Cimino, October 27, 2015: US09171901 (1 worldwide citation)

An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside ...


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Himadri Sekhar Pal, Youn Sung Choi, Amitabh Jain: Drain induced barrier lowering with anti-punch-through implant. Texas Instruments Incorporated, Jacqueline J Garner, Frederick J Telecky Jr, March 24, 2015: US08987748 (1 worldwide citation)

An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer prior to etching the source drain regions for epitaxial replacement. The anti-punch-through layer is disposed between stressor tips of the epit ...


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Himadri Sekhar Pal, Shashank S Ekbote, Youn Sung Choi: Integration of analog transistor. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, December 1, 2015: US09202810 (1 worldwide citation)

An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog trans ...


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Himadri Sekhar Pal, Shashank S Ekbote, Youn Sung Choi: Integration of analog transistor. TEXAS INSTRUMENTS INCORPORATED, Jacqueline J Garner, Frank D Cimino, August 9, 2016: US09412741 (1 worldwide citation)

An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog trans ...