1
Yoav Talgam, James A Klingshirn, James B Gullette: Cache which provides status information. Motorola, James L Clingan Jr, November 19, 1991: US05067078 (45 worldwide citation)

A first processing system is coupled to a plurality of integrated circuits along a P bus. Each of these integrated circuits has a combination cache and memory management unit (MMU). The cache/MMU integrated circuits are also connected to a main memory via an M bus. A second processing system is also ...


2
Yoav Talgam, Paul A Reed, Elie Haddad, James A Klingshirn: Diagnostic mode for a cache. Motorola, James L Clingan Jr, February 26, 1991: US04996641 (41 worldwide citation)

A cache has an address bus for receiving requests for data from a processor and a data bus for providing the requested data to the processor. As part of the mechanism for determining if there is a hit in the cache, the cache has TAG locations for storing TAG addresses. The hit signal is not generate ...


3
Mitchell Alsup, Yoav Talgam, Marvin A Denman: Method and apparatus for a data processor to support multi-mode, multi-precision integer arithmetic. Motorola, Robert L King, January 9, 1990: US04893267 (36 worldwide citation)

In a data processor having an integer arithmetic unit, the carry-in control logic, carry-out control logic, and the overflow control logic of the arithmetic unit are adapted to be directly controlled by respective carry-in enable, carry-out enable, and overflow enable fields of the integer arithmeti ...


4
Yoav Talgam, Mitch K Alsup, Marvin A Denman: Method and apparatus for handling out of order exceptions in a pipelined data unit. Motorola, Robert L King, February 20, 1990: US04903264 (29 worldwide citation)

A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechani ...


5
Denman Marvin A, Yoav Talgam: Method and apparatus for dynamically controlling each stage of a multi-stage pipelined data unit. Motorola, Robert L King, January 9, 1990: US04893233 (24 worldwide citation)

A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechani ...


6
Yoav Talgam, Mitch K Alsup, James A Klingshirn: Method and apparatus for explicitly evaluating conditions in a data processor. Motorola, April 3, 1990: US04914581 (3 worldwide citation)

In a data processor, the conditions associated with an operand are evaluated only in response to the execution of a special instruction. The results of this evaluation is provided as a result operand and stored in a general purpose destination register. The evaluated conditions are each provided in ...


7
Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James P Held: Instruction set architecture-based inter-sequencer communications with a heterogeneous resource. Intel Corporation, Trop Pruner & Hu P C, December 16, 2014: US08914618 (2 worldwide citation)

In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communicatio ...


8
Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James P Held: Instruction set architecture-based inter-sequencer communications with a heterogeneous resource. Intel Corporation, Trop Pruner & Hu P C, March 7, 2017: US09588771

In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communicatio ...


9
Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund, Dion Rodgers, Gautham Chinya, Baiju Patel, Shiv Kaushik, Bryant Bigbee, Gad Sheaffer, Yoav Talgam, Yuval Yosef, James P Held: Instruction set architecture-based inter-sequencer communications with a heterogeneous resource. Intel Corporation, Trop Pruner & Hu P C, October 4, 2016: US09459874

In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communicatio ...


10
Tamara Gaidar, Glen J Anderson, Yoav Talgam, Stephen Brown, Ido Lapidot, Oded Agam: Wearable electronic device to provide injury response. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 21, 2017: US09600995

Embodiments are generally directed to a wearable electronic device providing injury response. A wearable electronic device may include an injury detection unit that includes one or more sensors, and a central computing unit to receive sensor data from the one or more sensors to detect one or more in ...