1
Ying Yu Tai, Yueh Yale Ma: Soft information generation for memory systems. SANDISK ENTERPRISE IP, Morgan Lewis & Bockius, June 16, 2015: US09058289 (13 worldwide citation)

Implementations include systems, methods and/or devices suitable for use in a memory system that use error control codes to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate and utilize soft information fo ...


2
Ying Yu Tai, Seungjune Jeon, Jinagli Zhu, Yeuh Yale Ma: Method and system of reading threshold voltage equalization. SANDISK TECHNOLOGIES, Morgan Lewis & Bockius, September 27, 2016: US09454420 (6 worldwide citation)

The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. The method includes, in response to one or more host read commands, reading data from a set of memory cells in a flash memory ...


3
Ying Yu Tai, Yueh Yale Ma: Adaptive read comparison signal generation for memory systems. Sandisk Enterprise IP, Morgan Lewis & Bockius, July 29, 2014: US08793543 (5 worldwide citation)

Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate ...


4
Xiaoheng Chen, Jiangli Zhu, Ying Yu Tai: Syndrome layered decoding for LDPC codes. SANDISK ENTERPRISE IP, Morgan Lewis & Bockius, September 15, 2015: US09136877 (2 worldwide citation)

The various implementations described herein include systems, methods and/or devices for enhancing the performance of error control decoding. The method includes receiving at an LDPC decoder data from a storage medium corresponding to N variable nodes. The method further includes: updating a subset ...


5
Ying Yu Tai, Yueh Yale Ma: Statistical read comparison signal generation for memory systems. Sandisk Enterprise IP, Morgan Lewis & Bockius, January 20, 2015: US08938658 (2 worldwide citation)

Implementations include systems, methods and/or devices suitable for use in a memory system that may enhance the performance of error control codes used to improve the reliability with which data can be stored and read. Some implementations include systems, methods and/or devices enabled to generate ...


6
Jiangli Zhu, Ying Yu Tai, Xiaoheng Chen: Universal and reconfigurable QC-LDPC encoder. SANDISK ENTERPRISE IP, Morgan Lewis & Bockius, January 12, 2016: US09236886

The various implementations described herein include systems, methods and/or devices that may enhance performance of error control encoding. The method includes receiving information data and generating parity information based on an m×k parity matrix comprising an array of b×b circulant sub-matrice ...


7
Xiaoheng Chen, Ying Yu Tai, Jiangli Zhu, Seungjune Jeon: Compressing data from multiple reads for error control management in memory systems. SANDISK ENTERPRISE IP, Morgan Lewis & Bockius, January 19, 2016: US09239751

The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. Some implementations include a method of compressing a sequence of read data values into a bit-tuple of a predefined length t ...


8
Xiaoheng Chen, Jingyu Kang, Jiangli Zhu, Ying Yu Tai: Method and system for determining soft information offsets. SANDISK TECHNOLOGIES, Morgan Lewis & Bockius, May 9, 2017: US09647697

Systems, methods, and/or devices are used to improve decoding of data read from a storage device with one or more memory devices. In one aspect, the method includes obtaining, in response to a read request, a codeword with two or more codeword portions from distinct memory portions of the storage de ...


9
Xinmiao Zhang, Ying Yu Tai: High-speed multi-block-row layered decoder for low density parity check (LDPC) codes. SANDISK TECHNOLOGIES, Toler Law Group PC, March 21, 2017: US09602141

High-speed multi-block-row layered decoding for low density parity check (LDPC) codes is disclosed. In a particular embodiment, a method, in a device that includes a decoder configured to perform an iterative decoding operation, includes processing, at the decoder, first and second block rows of a l ...


10
Xinmiao Zhang, Ying Yu Tai: Encoder for quasi-cyclic low-density parity-check codes over subfields using fourier transform. SANDISK TECHNOLOGIES, Toler Law Group PC, August 30, 2016: US09432055

A quasi-cyclic low-density parity-check (QC-LDPC) encoder includes a Fourier transform circuit configured to receive an input message and to generate a transformed message based on the input message. The transformed message includes leading symbols with indices corresponding to leading elements of c ...