1
Masami Masuda, Yasumitsu Nozawa, Takayuki Kawaguchi: BiMOS logical circuit. Kabushiki Kaisha Toshiba, Foley & Lardner Schwartz Jeffery Schwaab Mack Blumenthal & Evans, February 14, 1989: US04804869 (20 worldwide citation)

The invention is a BiMOS logical circuit having a reduced number of components and increased operating speed. First and second MOS transistors are provided for, respectively, driving first and second bipolar transistors. The gates of these MOS transistors are, respectively, connected to the bases of ...


2
Takayuki Kawaguchi, Shigeto Mizukami, Yasumitsu Nozawa, Kouji Nakao: Semiconductor memory device having bit line equalizing means. Kabushiki Kaisha Toshiba, Foley & Lardner, January 23, 1996: US05487044 (18 worldwide citation)

A semiconductor memory device having memory cells arranged in a matrix, each of the memory cells having input/output terminals, word lines for selecting the memory cells, pairs of bit lines connected to the input/output terminals, bit line pulling-up means for pulling up the potential of the bit lin ...


3
Masami Masuda, Takayuki Kawaguchi, Yasumitsu Nozawa: BiMOS logical circuit. Kabushiki Kaisha Toshiba, Foley & Lardner Schwartz Jeffery Schwaab Mack Blumenthal & Evans, February 14, 1989: US04804868 (17 worldwide citation)

This invention is a BiMOS logical circuit that provides a suitable output level with a limited number of components. The intermediate node of a PMOS transistor and an NMOS transistor is connected to the base of a bipolar transistor to control output voltage. The NMOS transistor is connected between ...


4
Yasumitsu Nozawa, Shigeto Mizukami, Makoto Segawa: Semiconductor integrated circuit for a stable constant delay time. Kabushiki Kaisha Toshiba, Foley & Lardner, October 17, 1995: US05459423 (10 worldwide citation)

A delay circuit is interposed between first and second circuit systems both driven by a first supply voltage. The delay circuit delays a signal applied by the first circuit system, and then transmits the delayed signal to the second circuit system. In particular, a constant voltage supply circuit ge ...


5
Akihiro Mishima, Yoichi Suzuki, Yasumitsu Nozawa, Masami Masuda: Semiconductor memory device and method relieving defect of semiconductor memory device. Kabushiki Kaisha Toshiba, Loeb & Loeb, January 25, 2000: US06018488 (9 worldwide citation)

A semiconductor memory device includes bit lines and word lines arranged lengthwise and breadthwise, memory cells 1 capable of reading out and writing in, MOS transistors Q1 and Q2 for pre-charge, MOS transistors Q3 for short-circuiting, and transistors Q4 and Q5 for setting voltage level. The bit l ...


6
Yasumitsu Nozawa, Kenichi Nakamura, Takayuki Otani, Makoto Segawa: Semiconductor device and SRAM having plural power supply voltages. Kabushiki Kaisha Toshiba, Loeb & Loeb, October 20, 1998: US05825707 (6 worldwide citation)

A semiconductor device comprises: a first circuit (11) formed in a first well (N-type) and a second well (P-type) of a semiconductor substrate, supplied with a first supply voltage (V.sub.ss) and a second supply voltage (V.sub.cc) higher than the first supply voltage, and activated when a first well ...


7
Takayuki Otani, Yasumitsu Nozawa, Satoru Hoshi: Semiconductor memory device. Kabushiki Kaisha Toshiba, Loeb & Loeb, October 12, 1999: US05966333 (5 worldwide citation)

A semiconductor memory device includes normal row selection lines (NWL1 to NWL128) for selecting one of normal rows, a spare row selection line (SWL) for selecting a spare row instead when one of the normal rows has a defect, fuses (F1 to F128) which are respectively arranged on the normal row selec ...