1
Yasuhiro Konishi, Takayuki Miyamoto, Takeshi Kajimoto, Hisashi Iwamoto: Synchronous semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, January 24, 1995: US05384745 (277 worldwide citation)

Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines ar ...


2
Yasumitsu Murai, Hisashi Iwamoto, Yasuhiro Konishi, Naoya Watanabe, Seiji Sawada: Synchronous type semiconductor memory device operating in synchronization with an external clock signal. Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering, Lowe Price LeBlanc & Becker, April 4, 1995: US05404338 (132 worldwide citation)

In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in ...


3
Yasuhiro Konishi, Hisashi Iwamoto, Takashi Araki, Yasumitsu Murai, Seiji Sawada: Synchronous semiconductor memory device and synchronous memory module. Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering, McDermott Will & Emery, September 29, 1998: US05815462 (99 worldwide citation)

A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and ...


4
Yasuhiro Konishi, Takayuki Miyamoto, Takeshi Kajimoto, Hisashi Iwamoto: Synchronous semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, January 14, 1997: US05594704 (67 worldwide citation)

Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines ar ...


5
Takahiro Komatsu, Masaki Kumanoya, Katsumi Dosaka, Yasuhiro Konishi: Self-refreshing of dynamic random access memory device and operating method therefor. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc Becker & Shur, July 24, 1990: US04943960 (66 worldwide citation)

There is disclosed a dynamic random access memory device of the type capable of periodic self-refresh cycles of operation. The DRAM includes the detector circuit for detecting the designation of the self-refresh mode and a voltage generator circuit for generating a voltage to precharge the bit line ...


6
Masaki Kumanoya, Yasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Youichi Tobita: Substrate bias potential generator of a semiconductor integrated circuit device and a generating method therefor. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc Becker & Shur, October 2, 1990: US04961007 (65 worldwide citation)

A substrate bias potential generator for biasing a semiconductor substrate to a predetermined potential includes first and second substrate bias generating circuits which operate alternatively according to the potential of the substrate, whereby consumption of power in the substrate bias potential g ...


7
Hisashi Iwamoto, Yasuhiro Konishi: Synchronous semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, January 13, 1998: US05708611 (65 worldwide citation)

A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal c ...


8
Masaaki Tanimura, Yasuhiro Konishi: Synchronous semiconductor memory device in which current consumed by input buffer circuit is reduced. Mitsubishi Denki Kabushiki Kaisha, McDermott Will & Emery, March 9, 1999: US05880998 (62 worldwide citation)

An external clock enable signal is taken in accordance with a first internal clock signal from clock buffer circuit from which an input buffer enable signal is generated to be input to input buffer circuit. Current path in the input buffer circuit is shut off in accordance with the input buffer enab ...


9
Masaki Kumanoya, Katsumi Dosaka, Yasuhiro Konishi, Hiroyuki Yamasaki, Takahiro Komatsu, Yoichi Tobita: Dynamic random access memory device and operating method therefor. Mitsubishi Denki Kabushiki Kaisha, Lowe Price Leblanc Becker & Shur, June 12, 1990: US04933907 (58 worldwide citation)

A dynamic random access memory having a self-refresh mode comprises a memory array partitioned into four groups in which control are respectively performed and a partial activation control circuit. The four groups in the memory array are alternately refreshed two by two in an operation under the sel ...


10
Seiji Sawada, Yasuhiro Konishi: Test circuit for refresh counter of clock synchronous type semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, November 28, 1995: US05471430 (53 worldwide citation)

A synchronous semiconductor memory device includes an automatic refresh detection circuit for detecting that an automatic refresh mode is specified in accordance with an automatic refresh command, an address counter for generating a refresh address, a refresh execution unit for refreshing a memory a ...