1
Le Trong Nguyen, Derek J Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te Li Lau, Sze Shun Wang, Quang H Trang: High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox P L L C, September 24, 1996: US05560032 (112 worldwide citation)

A high-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution for enhanced resource utilization and performance throughput. The computer system architecture includes an instruction fetch unit for fetching program instruction sets. E ...


2
Derek J Lentz, Yasuaki Hagiwara, Te Li Lau, Cheng Long Tang, Le Trong Nguyen: Microprocessor architecture capable of supporting multiple heterogeneous processors. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox P L L C, August 7, 2001: US06272579 (85 worldwide citation)

A system and method for transferring data in a multiprocessor architecture capable of supporting multiple processors. The system comprises a priority assignor that provides a dynamic priority to input/output unit (IOU), D-cache and I-cache devices requests as a function of an intrinsic priority assi ...


3
Derek J Lentz, Yasuaki Hagiwara, Te Li Lau, Cheng Long Tang, Le Trong Nguyen: Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox, August 8, 1995: US05440752 (84 worldwide citation)

A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory am handled using a switch network. Access to memory buses is controlled by arbitration circuits which utilize fixed and ...


4
Le T Nguyen, Derek J Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te Li Lau, Sze Shun Wang, Quang H Trang: High-performance, superscalar-based computer system with out-of-order instruction execution. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox, July 23, 1996: US05539911 (81 worldwide citation)

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a s ...


5
Le Trong Nguyen, Derek J Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te Li Lau, Sze Shun Wang, Quang H Trang: High performance, superscalar-based computer system with out-of-order instruction execution. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox P L L C, October 5, 1999: US05961629 (70 worldwide citation)

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system ...


6
Le Trong Nguyen, Derek J Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Te Li Lau, Sze Shun Wang, Quang H Trang: High-performance superscalar-based computer system with out-of-order instruction execution. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox P L L C, November 18, 1997: US05689720 (64 worldwide citation)

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a s ...


7
Le T Nguyen, Derek J Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Quang Trang: RISC microprocessor architecture implementing fast trap and exception state. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox, September 5, 1995: US05448705 (53 worldwide citation)

A method for use in a microprocessor to return execution to a main program after processing an interruption to the sequential processing of instructions from the main instruction stream is disclosed. The method comprises fetching instructions from a main instruction stream to a main buffer section o ...


8
Derek J Lentz, Yasuaki Hagiwara, Te Li Lau, Cheng Long Tang, Le Trong Nguyen: Microprocessor architecture capable of supporting multiple heterogeneous processors. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox P L L C, August 26, 2003: US06611908 (48 worldwide citation)

A memory control unit for controlling access, by one or more devices within a processor, to a memory array unit external to the processor via one or more memory ports of the processor. The memory control unit includes a switch network to transfer data between the one or more devices of the processor ...


9
Le T Nguyen, Derek J Lentz, Yoshiyuki Miyayama, Sanjiv Garg, Yasuaki Hagiwara, Johannes Wang, Quang Trang: RISC microprocessor architecture implementing fast trap and exception state. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox, January 2, 1996: US05481685 (46 worldwide citation)

Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be locate ...


10
Derek J Lentz, Yasuaki Hagiwara, Te Li Lau, Cheng Long Tang, Le Trong Nguyen: Multi processor system having dynamic priority based on row match of previously serviced address, number of times denied service and number of times serviced without interruption. Seiko Epson Corporation, Sterne Kessler Goldstein & Fox P L L C, May 19, 1998: US05754800 (45 worldwide citation)

A computer system comprising a multiprocessor architecture capable of supporting multiple processors comprising a memory array unit (MAU), an MAU system bus comprising data, address and control signal buses, an I/O bus comprising data, address and control signal buses, a plurality of I/O devices and ...