1
Hung Cheng Sung, Di Son Kuo, Chia Ta Hsieh, Yai Fen Lin: Poly tip formation and self-align source process for split-gate flash cell. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, September 12, 2000: US06117733 (32 worldwide citation)

A novel method of forming a first polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notch in two different ways in a nitride layer overlying the first polysilicon layer. In one embodiment, the notch ...


2
Chia Ta Hsieh, Hung Cheng Sung, Yai Fen Lin, Jack Yeh, Di Son Kuo: Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, Sevgin Oktay, May 8, 2001: US06228695 (32 worldwide citation)

A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate followed by ...


3
Chia Ta Hsieh, Yai Fen Lin, Di Son Kuo, Hung Cheng Sung, Jack Yeh: Method to increase coupling ratio of source to floating gate in split-gate flash. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, December 12, 2000: US06159801 (29 worldwide citation)

A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling w ...


4
Chia Ta Hsieh, Yai Fen Lin, Hung Cheng Sung, Chuang Ke Yeh, Di Son Kuo: Method of fabricating step poly to improve program speed in split gate flash. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, March 9, 1999: US05879992 (23 worldwide citation)

A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched t ...


5
Chia Ta Hsieh, Yai Fen Lin, Di Son Kuo, Hung Cheng Sung, Jack Yeh: Method to increase coupling ratio of source to floating gate in split-gate flash. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, Sevgin Oktay, April 30, 2002: US06380583 (22 worldwide citation)

A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling w ...


6
Chia Ta Hsieh, Di Son Kuo, Yai Fen Lin, Chrong Jung Lin, Jong Chen, Hung Der Su: Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, November 28, 2000: US06153494 (18 worldwide citation)

A method is provided for forming a stacked-gate flash memory cell having a shallow trench isolation with a high-step of oxide and high lateral coupling. This is accomplished by first depositing an unconventionally high or thick layer of nitride and then forming a shallow trench isolation (STI) throu ...


7
Yai Fen Lin, Shiou Hann Liaw, Di Son Kuo, Juang Ke Yeh: Method of manufacture of P-channel EEprom and flash EEprom devices. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, Graham S Jones II, May 9, 2000: US06060360 (16 worldwide citation)

A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can b ...


8
Yai Fen Lin, Chia Ta Hsieh, Hung Cheng Sung, Chuang Ke Yeh, Di Son Kuo: Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, April 4, 2000: US06046086 (16 worldwide citation)

A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split-gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the floating g ...


9
Chia Ta Hsieh, Hung Cheng Sung, Yai Fen Lin, Di Son Kuo: Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, January 12, 1999: US05858840 (16 worldwide citation)

A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory cell. This is accomplished by implanting nitrogen ions in the first polysilicon layer of the cell and removing them from the area where the floating gate is to be for ...


10
Hung Cheng Sung, Di Son Kuo, Yai Fen Lin, Chia Ta Hsieh: Program and erase method for a split gate flash EEPROM. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, Billy J Knowles, December 21, 1999: US06005809 (15 worldwide citation)

A method to program data to and erase data from a split gate flash EEPROM to improve programming and erasing speed, and to improve endurance is disclosed. The programming the split gate flash EEPROM cell is accomplished by simultaneously applying a first positive voltage to the control gate, applyin ...