1
Sanjay Mehrotra, Eliyahou Harari, Winston Lee: Multi-state EEprom read and write circuits and techniques. Sundisk Corporation, Majestic Parsons Siebert & Hsue, December 15, 1992: US05172338 (1028 worldwide citation)

Improvements in the circuits and techniques for read, write and erase of EEprom memory enable non-volatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading ...


2
Sanjay Mehrotra, Eliyahou Harari, Winston Lee: Multi-state EEprom read and write circuits and techniques. SunDisk Corporation, Majestic Parsons Siebert & Hsue, November 10, 1992: US05163021 (362 worldwide citation)

Improvements in the circuits and techniques for read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading i ...


3
Sanjay Mehrotra, Winston Lee, George Samachisa, Stephen J Gross: Latent defect handling in EEPROM devices. SunDisk Corporation, Majestic Parsons Siebert & Hsue, June 27, 1995: US05428621 (201 worldwide citation)

A memory system having a two dimensional array of EEPROM or Flash EEPROM cells is addressable by rows and columns. A word line is connected to the control gates of all the cells in each row, an erase line is connected to all the erase gates of each sector of cells, and a pair of bit lines are connec ...


4
Wingyu Leung, Winston Lee, Fu Chieh Hsu: Resynchronization circuit for a memory system and method of operating same. Monolithic System Technology, Skjerven Morrill MacPherson Franklin & Friel, August 5, 1997: US05655113 (165 worldwide citation)

A resynchronization circuit for processing a stream of data values read from a memory system, and a method of operating the same. The resynchronization circuit includes a first in, first out (FIFO) memory device, a phase locked loop circuit and a latency control circuit. The FIFO memory device recei ...


5
Wingyu Leung, Winston Lee, Fu Chieh Hsu: Memory array with read/write methods. Monolithic System Technology, E Eric Hoffman, Bever Hoffman & Harms, June 22, 2004: US06754746 (124 worldwide citation)

Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data ampl ...


6
Wingyu Leung, Winston Lee, Fu Chieh Hsu: Reduced CMOS-swing clamping circuit for bus lines. Monolithic System Technology, Norman R Klivans, E Eric Hoffman, Skjerven Morrill MacPherson Franklin & Friel, March 12, 1996: US05498990 (105 worldwide citation)

A memory system having several memory devices coupled to a memory controller through an I/O bus, each memory device including multiple memory modules coupled to a chip I/O interface through an internal bus. The system includes a circuit for driving the I/O bus with a reduced CMOS-swing, a circuit fo ...


7
Wingyu Leung, Winston Lee, Fu Chieh Hsu: Termination circuits for reduced swing signal lines and methods for operating same. Monolithic System Technology, Norman R Klivans, E Eric Hoffman, Skjerven Morrill MacPherson Franklin & Friel, March 17, 1998: US05729152 (35 worldwide citation)

A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwi ...


8
Wingyu Leung, Winston Lee, Fu Chieh Hsu: Dynamic address mapping and redundancy in a modular memory device. Monolithic System Technology, Skjerven Morrill MacPherson, May 21, 2002: US06393504 (35 worldwide citation)

A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a bus. Each memory module has independent address and command decoders to enable independent operation. Thus each memory module is activated by commands on the bus only when a memory acces ...


9
Sanjay Mehrotra, Winston Lee, George Samachisa, Stephen J Gross: Latent defect handling in EEPROM devices. SanDisk Corporation, Majestic Parsons Siebert & Hsue, August 19, 1997: US05659550 (34 worldwide citation)

A memory system having a two dimensional array of EEPROM or Flash EEPROM cells is addressable by rows and columns. A word line is connected to the control gates of all the cells in each row, an erase line is connected to all the erase gates of each sector of cells, and a pair of bit lines are connec ...


10
Eugene W Teglovic, John B Hedges, Douglas L Wekamp, Theresa R Jahelka, J Wilbur Wayne Whitney III, Winston Lee Davis Jr, Valerie J Prothe: System and method for real-time exchange of customer data between telecommunications companies (quick pic). MCI Communications Corporation, April 27, 1999: US05898765 (21 worldwide citation)

A system and method for real-time exchange of customer information between telecommunications companies provides a significant reduction in the time required for completing a preferred inter-exchange carrier (PIC) order. It also provides significant reductions in the time required for other applicat ...