1
James A Gasbarro, Mark A Horowitz, Richard M Barth, Winston K M Lee, Wingyu Leung, Paul M Farmwald: Method and circuitry for minimizing clock-data skew in a bus system. Rambus, Blakely Sokoloff Taylor & Zafman, July 11, 1995: US05432823 (327 worldwide citation)

A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnar ...


2
Mark A Horowitz, James A Gasbarro, Wingyu Leung: Electrical current source circuitry for a bus. Rambus, Blakely Sokoloff Taylor & Zafman, October 19, 1993: US05254883 (320 worldwide citation)

Electrical current source circuitry for a bus is described. The circuitry includes transistor circuitry coupled between the bus and ground for controlling bus current, control circuitry coupled to the transistor circuitry, and a controller coupled to the control circuitry for controlling the transis ...


3
Wingyu Leung, Mark A Horowitz: Method and circuitry for clock synchronization. Rambus, Blakely Sokoloff Taylor & Zafman, January 16, 1996: US05485490 (235 worldwide citation)

Circuitry for performing fine phase adjustment within a phase locked loop is described. The phase selector selects an even phase signal and an odd phase signal from the twelve phase signals output by the VCO. The even and odd phase signals are selected by an even select signal and an odd select sign ...


4
Wingyu Leung, Winston Lee, Fu Chieh Hsu: Resynchronization circuit for a memory system and method of operating same. Monolithic System Technology, Skjerven Morrill MacPherson Franklin & Friel, August 5, 1997: US05655113 (164 worldwide citation)

A resynchronization circuit for processing a stream of data values read from a memory system, and a method of operating the same. The resynchronization circuit includes a first in, first out (FIFO) memory device, a phase locked loop circuit and a latency control circuit. The FIFO memory device recei ...


5
Wingyu Leung, Fu Chieh Hsu: Method and structure for implementing a cache memory using a DRAM array. Monolithic System Technology, Norman R Klivans, Skjerven Morrill MacPherson Franklin & Friel, October 27, 1998: US05829026 (136 worldwide citation)

A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and a second level cache memory which includes a DRAM array co ...


6
Wingyu Leung: High density SRAM circuit with ratio independent memory cells. Integrated Device Technology, Thomas E Schatzel, September 10, 1991: US05047979 (127 worldwide citation)

Briefly, a high density, static, random access memory (SRAM) circuit with ratio independent memory cells employs a number (plurality) of (4T-2R) or (6T) type SRAM cells and a regenerative sense amplifier. Each of the SRAM cells of the present invention differs from corresponding, prior art type SRAM ...


7
Wingyu Leung, Fu Chieh Hsu: Fault-tolerant hierarchical bus system and method of operating same. Monolithic System Technology, Norman R Klivans Jr, E Eric Hoffman, Skjerven Morrill MacPherson Franklin & Friel, September 9, 1997: US05666480 (121 worldwide citation)

A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together ...


8
Wingyu Leung, Winston Lee, Fu Chieh Hsu: Reduced CMOS-swing clamping circuit for bus lines. Monolithic System Technology, Norman R Klivans, E Eric Hoffman, Skjerven Morrill MacPherson Franklin & Friel, March 12, 1996: US05498990 (105 worldwide citation)

A memory system having several memory devices coupled to a memory controller through an I/O bus, each memory device including multiple memory modules coupled to a chip I/O interface through an internal bus. The system includes a circuit for driving the I/O bus with a reduced CMOS-swing, a circuit fo ...


9
Fu Chieh Hsu, Wingyu Leung: Circuit module redundancy architecture process. Monolithic System Technology, Skjerven Morrill MacPherson Franklin & Friel, December 1, 1998: US05843799 (102 worldwide citation)

A system and method for wafer scale integration optimized for medium die size integrated circuits by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor wafer so as to electrically exclude both defective modules and defective interconnect/power segments, a ...


10
Wingyu Leung, Fu Chieh Hsu: High density SRAM circuit with single-ended memory cells. Monolithic System Technology, Skjerven Morrill MacPherson Franklin & Friel, November 23, 1993: US05265047 (98 worldwide citation)

A high density, static random access memory (SRAM) circuit with single-ended memory cells employs a plurality of (4T-2R) or (6T) type SRAM cells and a regenerative sense amplifier. Each of the SRAM cells employs a single bit-line (BL) and two word lines.