1
Danesh Tavana, Wilson K Yee, Stephen M Trimberger: Integrated circuit with field programmable and application specific logic areas. Xilinx, Edel M Young, Adam H Tachner, Lois D Cartier, October 20, 1998: US05825202 (235 worldwide citation)

A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By int ...


2
Danesh Tavana, Wilson K Yee, Victor A Holen: FPGA architecture with repeatable tiles including routing matrices and logic matrices. Xilinx, Edel M Young, Norman R Skjerven Morrill MacPherson Franklin & Friel Klivans, October 28, 1997: US05682107 (202 worldwide citation)

An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matr ...


3
Danesh Tavana, Wilson K Yee, Victor A Holen: FPGA architecture with repeatable titles including routing matrices and logic matrices. Xilinx, Edel M Young, March 16, 1999: US05883525 (165 worldwide citation)

An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matr ...


4
Danesh Tavana, Wilson K Yee, Stephen M Trimberger: Integrated circuit with field programmable and application specific logic areas. Xilinx, Edel M Young, Scott R Brown Esq, July 25, 2000: US06094065 (111 worldwide citation)

A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By int ...


5
Wilson K Yee: Programmable scan chain testing structure and method. Xilinx, Edel M Young, August 27, 1996: US05550843 (31 worldwide citation)

A circuit and method for testing Field Programmable Gate Arrays (FPGAs) comprises a programmable multiplexer for sequentially connecting columns of logic cells to enable the configuring of logic cell columns into one or more scan chains. Each column of logic cells contains an edge cell comprising a ...


6
Wilson K Yee: Programmable scan chain testing structure and method. Xilinx, Edel M Young, Leroy D Maunu Esq, October 7, 1997: US05675589 (23 worldwide citation)

A circuit and method for testing Field Programmable Gate Arrays (FPGAs) comprises a programmable multiplexer for sequentially connecting columns of logic cells to enable the configuring of logic cell columns into one or more scan chains. Each column of logic cells contains an edge cell comprising a ...


7
Wilson K Yee: Field programmable gate array providing contention free configuration and reconfiguration. Xilinx, Edel M Young, September 26, 1995: US05453706 (16 worldwide citation)

A circuit and method in a field programmable gate array (FPGA) for eliminating programming contentions which occur during array configuration comprises a switching matrix of crossing lines, in which cross points, called programmable interconnection points (PIPs), are connected by configuration trans ...


8
Steven P Young, Jane W Sowards, Wilson K Yee: Structure and method for generating a clock enable signal in a PLD. Xilinx, Lois D Cartier, April 17, 2001: US06218864 (15 worldwide citation)

The invention provides a structure and method of generating a clock enable signal in a programmable logic device (PLD). A first embodiment of the invention comprises a clock enable circuit implemented such that the critical paths have only two levels of logic. In this embodiment, the critical paths ...


9
Joseph I Chamdani, Litko Chan, Richard D Reohr Jr, Wilson K Yee: Processing data packets at a storage service module of a switch. Brocade Communications Systems, Hensley Kim & Holzer, December 2, 2008: US07460528 (6 worldwide citation)

Routing a data packet of an information unit sequence includes receiving at a switch a data packet of an information unit sequence of a block storage exchange from a storage client, where the sequence is associated with a source identifier and a target identifier identifying a target. A storage reso ...


10
Scott O Frake, James L McManus, David P Schultz, Wilson K Yee: Method and system for PLD swapping. Xilinx, Jeanette S Harms, John Kubodera, Edel M Young, February 25, 2003: US06526466 (3 worldwide citation)

An apparatus and method for enabling hot swapping of programmable logic devices (PLDs) and boards containing PLDs is provided. If the hot swap capability is desired, a hot swap terminal on the PLD is set to facilitate a floating state on the input/output pad of the PLD. Further, the input buffer and ...