1
Hoffman William Wheeler, Kraska Allen Richard: Carboxylic acid derivatives useful for inhibiting the degradation of cartilage.. Pfizer, January 9, 1985: EP0130795-A2 (154 worldwide citation)

Certain carboxylic acids of the formula and the pharmaceutically-acceptable salts thereof, and certain esters and amides thereof, are useful for inhibiting the degradation of articular cartilage when administered to a mammalian subject afflicted with an arthritic disease. X is O, S, SO, SO2, NH, NCH ...


2
Matthew J Adiletta, Gilbert Wolrich, William Wheeler: Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode. Intel Corporation, Fish & Richardson P C, August 12, 2003: US06606704 (134 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory con ...


3
Gilbert Wolrich, Debra Bernstein, Donald Hooper, Matthew J Adiletta, William Wheeler: Thread signaling in multi-threaded network processor. Intel Corporation, Fish & Richardson P C, September 23, 2003: US06625654 (120 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory cont ...


4
Debra Bernstein, Donald F Hooper, Matthew J Adiletta, Gilbert Wolrich, William Wheeler: Microengine for parallel processor architecture. Intel Corporation, Fish & Richardson P C, December 23, 2003: US06668317 (112 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory con ...


5
Matthew J Adiletta, William Wheeler, James Redfield, Daniel Cutter, Gilbert Wolrich: SRAM controller for parallel processor architecture including address and command queue and arbiter. Intel Corporation, Fish & Richardson P C, July 30, 2002: US06427196 (106 worldwide citation)

A controller for a random access memory includes an address and command queue that holds memory references from a plurality of micro control functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue ...


6
Gilbert Wolrich, Debra Bernstein, Matthew J Adiletta, William Wheeler: Arbitrating command requests in a parallel multi-threaded processing system. Intel Corporation, Fish & Richardson P C, March 11, 2003: US06532509 (88 worldwide citation)

A parallel, multi-threaded processor system and technique for arbitrating command requests is described. The system includes a plurality of microengines, a plurality of shared system resources and a global command arbiter. The global command arbiter uses a command request protocol that is based on t ...


7
Matthew J Adiletta, William Wheeler, James Redfield, Daniel Cutter, Gilbert Wolrich: SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues. Intel Corporation, Fish & Richardson P C, April 27, 2004: US06728845 (80 worldwide citation)

A controller for a random access memory (RAM), such as a static ram (SRAM), includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller als ...


8
Gilbert Wolrich, Debra Bernstein, Matthew J Adiletta, William Wheeler: Handling contiguous memory references in a multi-queue system. Intel Corporation, Fish & Richardson P C, May 6, 2003: US06560667 (74 worldwide citation)

A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit th ...


9
Gilbert Wolrich, Daniel Cutter, William Wheeler, Matthew J Adiletta, Debra Bernstein: Read lock miss control and queue management. Intel Corporation, Fish & Richardson P C, November 27, 2001: US06324624 (68 worldwide citation)

Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if (1) the read lock memory reference request is requesting access to an unlocked memory location and (2) the ...


10
Gilbert Wolrich, Matthew J Adiletta, William Wheeler, Daniel Cutter, Debra Bernstein: Memory shared between processing threads. Intel Corporation, Fish & Richardson P C, October 7, 2003: US06631462 (66 worldwide citation)

A method includes pushing a datum onto a stack by a first processor and popping the datum off the stack by a second processor.