1
John E Campbell, William T Devine, Kris V Srikrishnan: Method and structure for buried circuits and devices. International Business Machines Corporation, Ira D Blecker, November 28, 2006: US07141853 (187 worldwide citation)

A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein ...


2
John E Campbell, William T Devine, Kris V Srikrishnan: Method and structure for buried circuits and devices. International Business Machines Corporation, Fred Gibb, Margaret A Pepper, McGinn & Gibb, July 6, 2004: US06759282 (116 worldwide citation)

A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein ...


3
William T Devine, William Gianopulos: Demand powered programmable logic array. International Business Machines Corporation, James E Murray, November 11, 1980: US04233667 (87 worldwide citation)

This specification describes a programmable logic array (PLA) for performing logic functions on binary variables in a plurality of sequentially functioning arrays in which at least one of the arrays is conditionally powered when and only when the binary variables are supplied to the PLA in a logical ...


4
Dennis T Cox, William T Devine, Gilbert J Kelly: High density logic array. International Business Machines Corporation, James E Murray, October 19, 1976: US03987287 (51 worldwide citation)

This specification describes arrays for performing logic functions. In these arrays, input variables can be fed to either or both ends of input lines. When input variables are fed to both ends of a line, the line is broken to separate logic performed on the variables fed to one end from the logic pe ...


5
Dennis T Cox, William T Devine, Gilbert J Kelly: Segmented parallel rail paths for input/output signals. IBM Corporation, James E Murray, February 3, 1976: US03936812 (31 worldwide citation)

This specification describes an orderly arrangement of input and output lines for a programmable logic array chip (PLA). In the arrangement, a plurality of parallel current conducting lines called rails are positioned on the chip along side the arrays of the PLA. The inputs and outputs of the arrays ...


6
John E Campbell, William T Devine, Sebastian T Ventrone: Dynamic object-level code transaction for improved performance of a computer. International Business Machines Corporation, Connolly Bove Lodge & Hutz, Anthony Canale, August 26, 2008: US07418580 (13 worldwide citation)

A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translat ...


7
William T Devine, William F Washburn: Logical OR circuit for programmed logic arrays. International Business Machines Corporation, Karl O Hesse, October 31, 1978: US04123669 (11 worldwide citation)

An improved logical OR circuit is shown wherein the load resistance is divided into drain resistance and source resistance, each resistance having a lower value than could be employed with a single load resistance while at the same time keeping power dissipation to low levels. The use of relatively ...


8
William T Devine, Jeffrey A Kash, John U Knickerbocker, Steven P Ostrander, Jeannine M Trewhella, Ronald P Luijten: Redundant configurable VCSEL laser array optical light source. International Business Machines Corporation, James J Cioffi Esq, Scully Scott Murphy & Presser, November 23, 2004: US06821026 (11 worldwide citation)

A redundant configurable VCSEL laser array optical light source which provides for integrating optical communications capabilities into manufacturing processes for a substrate or submount such as a silicon or ceramic substrate, a multi-chip module, a package board, backplane or similar component. Mu ...


9
John E Campbell, William T Devine, Kris V Srikrishnan: Method and structure for buried circuits and devices. International Business Machines Corporation, Wenjie Li, Daryl Neff, Ira D Blecker, February 17, 2009: US07491588 (10 worldwide citation)

A method is provided in which for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate. A plurality of field effect transistors (FETs) are formed, each having a channel region disposed in a common device layer within a single-crystal se ...


10
John E Campbell, William T Devine, Kris V Srikrishnan: Method and structure for buried circuits and devices. International Business Machines Corporation, Wenjie Li, Ira D Blecker, Mark R Bilak, January 22, 2008: US07320918 (9 worldwide citation)

A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein ...