1
Lydia Breck, Jessica Zoob, Glen Salow, Fred Bishop, William Schwarz, Elliot Glazer, David Johnstone, Katie Cunningham, Anant Nambiar, Jan Nunney Belt, Martin Wittwer, David Armes, Christina Chow: System for facilitating a transaction. American Express Travel Related Services Company, Fitzpatrick Cella Harper & Scinto, December 1, 2009: US07627531 (136 worldwide citation)

The present invention provides a system and method for facilitating a transaction using a secondary transaction number that is associated with a cardholder's primary account. The cardholder provides the secondary transaction number, often with limited-use conditions associated therewith, to a mercha ...


2
Lydia Breck, Jessica Zoob, Glen Salow, Fred Bishop, William Schwarz, Elliot Glazer, David Johnstone, Katie Cunningham, Anant Nambiar, Jan Nunney Belt, Martin Wittwer, David Armes, Christina Chow: System for facilitating a transaction. American Express Travel Related Services Company, Snell & Wilmer L, November 16, 2010: US07835960 (78 worldwide citation)

The present invention provides a system and method for facilitating a transaction using a secondary transaction number that is associated with a cardholder's primary account. The cardholder provides the secondary transaction number, often with limited-use conditions associated therewith, to a mercha ...


3
William Schwarz: Refresh sampling built-in self test and repair circuit. LSI Logic Corporation, B Noel Kivlin, Conley Rose & Tayon PC, June 1, 1999: US05909404 (48 worldwide citation)

A method for testing a memory device which statistically characterizes the failure time for a subset of cells sampled from the memory array before performing testing of the memory array in general. The memory device includes a testing unit which determines the failure times for cells in the sample s ...


4
Ghasi R Agrawal, Mukesh K Puri, William Schwarz: Method and system for performing built-in self-test routines using an accumulator to store fault information. LSI Corporation, Suiter Swantz PC LLO, August 21, 2007: US07260758 (34 worldwide citation)

A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the mem ...


5
William Schwarz, V Swamy Irrinki: Built-in self-test unit having a reconfigurable data retention test. LSI Logic Corporation, July 3, 2001: US06255836 (26 worldwide citation)

An integrated circuit device is disclosed having a BIST Uinit with recolfiLgurable data retention testing for a memory array. In one embodiment, the integrated circuit device includes a memory array, a BIST unit, an externally-programmable pause count register, and a pause counter. The BIST unit is ...


6
Tuan Phan, William Schwarz: Multi-condition BISR test mode for memories with redundancy. LSI Logic Corporation, Conley Rose & Tayon, January 7, 2003: US06505313 (24 worldwide citation)

A memory device configured to detect changes in fault patterns is disclosed. In one embodiment, the memory device includes a memory array, a built-in self-test (BIST) unit, and a built-in self-repair (BISR) unit. The BIST unit runs test patterns on the memory array to identify faulty locations in th ...


7
William Schwarz: Reconfigurable built-in self test circuit. LSI Logic Corporation, B Noel Kivlin, Raiph Veseli, Conley Rose & Tayon PC, November 9, 1999: US05982681 (20 worldwide citation)

A reconfigurable built-in self test circuit for enabling the debugging of an embedded device. In one embodiment, the write data path from the built-in self test module to the embedded device includes a multiplexer which is controlled by a debug signal. When the debug signal is de-asserted, the multi ...


8
William Schwarz: Data retention weak write circuit and method of using same. LSI Logic Corporation, November 10, 1998: US05835429 (12 worldwide citation)

A test circuit is provided for detection of data retention faults and cell stability faults of a memory array, such as a static random access memory (SRAM). The memory array test circuit comprises a weak write test circuit, a memory array address decoder, a microprocessor and display unit. During te ...


9
Mukesh K Puri, Ghasi R Agrawal, William Schwarz: Method for testing semiconductor devices having built-in self repair (BISR) memory. LSI Logic Corporation, Maginot Moore & Beck, July 11, 2006: US07076699 (11 worldwide citation)

A method for testing semiconductor devices advantageously increases manufacturing yields. The method includes generating memory repair data for a wafer die by writing at least one predetermined digital bit pattern into a memory on the wafer die, reading the at least one predetermined digital bit pat ...


10
Ghasi R Agrawal, Mukesh K Puri, William Schwarz: Method and system for performing built-in-self-test routines using an accumulator to store fault information. LSI Corporation, Suiter Swantz PC LLO, February 17, 2009: US07493541 (11 worldwide citation)

A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the mem ...