1
Peter D MacWilliams, Norman J Rasmussen, Nicholas D Wade, William S F Wu: Method and apparatus for sharing a signal line between agents. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 29, 2000: US06112016 (65 worldwide citation)

Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three ...


2
Peter D MacWilliams, Norman J Rasmussen, Nicholas D Wade, William S F Wu: Method and apparartus for sharing a signal line between agents. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 13, 1998: US05822767 (46 worldwide citation)

Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three ...


3
Peter D MacWilliams, Norman J Rasmussen, Nicholas D Wade, William S F Wu: Scalable cache attributes for an input/output bus. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 22, 1997: US05651137 (30 worldwide citation)

Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three ...