1
William M Johnson: System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache. Advanced Micro Devices, Foley & Lardner, August 4, 1992: US05136697 (274 worldwide citation)

A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate the address ...


2
David B Witt, William M Johnson: High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin & Friel, July 22, 1997: US05651125 (229 worldwide citation)

A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and lo ...


3
William M Johnson: Multiple instruction decoder for minimizing register port requirements. Advanced Micro Devices, Foley & Lardner, July 7, 1992: US05129067 (220 worldwide citation)

A multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read port contentions by the N register-operand ide ...


4
Gigy Baror, Brian W Case, Rod G Fleck, Philip M Freidin, Smeeta Gupta, William M Johnson, Cheng Gang Kong, Ole H Moller, Timothy A Olson, David I Sorensen: Streamlined instruction processor. Advanced Micro Devices, Fliesler Dubb Meyer & Lovejoy, May 15, 1990: US04926323 (137 worldwide citation)

A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions fr ...


5
William M Johnson, Timothy A Olson, Drew J Dutton, Sherman Lee, David W Stoenner: Direct memory access apparatus and methods for transferring data between buses having different performance characteristics. Advanced Micro Devices, Joseph J Kaliko, J Vincent Tortolano, October 31, 1989: US04878166 (92 worldwide citation)

Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More p ...


6
Gigy Baror, William M Johnson: Programmable cache memory as well as system incorporating same and method of operating programmable cache memory. Advanced Micro Device, Lowe Price LeBlanc & Becker, February 9, 1993: US05185878 (78 worldwide citation)

Methods and apparatus are disclosed for realizing an integrated cache unit (ICU) comprising both a cache memory and a cache controller on a single chip. The novel ICU is capable of being programmed, supports high speed data and instruction processing applications in both Reduced Instruction Set Comp ...


7
William M Johnson, David B Witt: Processing system for providing an in circuit emulator with processor internal state. Advanced Micro Devices, Foley & Lardner, October 18, 1994: US05357626 (77 worldwide citation)

A processing system is configured for providing an external in circuit emulator with an internal execution state resulting from the execution by a first processor of an internal instruction stored in an internal instruction cache. The processing system includes a second processor which includes an i ...


8
William M Johnson, Gigy Baror: High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure. Advanced Micro Devices, Joseph J Kaliko, J Vincent Tortulano, July 25, 1989: US04851990 (76 worldwide citation)

Methods and apparatus for realizing a high performance interface between a processor, constituting part of a reduced instruction set computer (RISC) system, and a set of devices, including memory means. According to the invention, the interface includes three independent buses. A shared processor ou ...


9
William M Johnson: Input/output controller incorporating address mapped input/output windows and read ahead/write behind capabilities. Advanced Micro Devices, H Donald Nelson, Mikio Ishimaru, Stephen A Becker, August 7, 1990: US04947366 (61 worldwide citation)

Methods and apparatus are set forth for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. The af ...


10
David B Witt, William M Johnson: Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction. Advanced Micro Devices, Lawrence J Merkel, Conley Rose & Tayon PC, July 3, 2001: US06256728 (61 worldwide citation)

A processor is configured to detect a branch instruction have a forward branch target address within a predetermined range of the branch fetch address of the branch instruction. If the branch instruction is predicted taken, instead of canceling subsequent instructions and fetching the branch target ...