1
Rick Lake
Warren M Farnworth, Rick C Lake, William M Hiatt: Microfeature workpieces having alloyed conductive structures, and associated methods. Micron Technology, Perkins Coie, January 28, 2014: US08637994

Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a target location of a microfeature workpiece, with the volume of material including at least a first metallic cons ...


2
Rick Lake
Warren M Farnworth, Rick C Lake, William M Hiatt: Microfeature workpieces having alloyed conductive structures, and associated methods. Micron Technology, January 3, 2013: US20130004792-A1

Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a target location of a microfeature workpiece, with the volume of material including at least a first metallic cons ...


3
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Multi-dice chip scale semiconductor components and wafer level methods of fabrication. Micron Technology, Stephen A Gratton, January 11, 2005: US06841883 (389 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


4
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Semiconductor component having plate, stacked dice and conductive vias. Micron Technology, Stephen A Gratton, March 3, 2009: US07498675 (94 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


5
Alan G Wood, William M Hiatt, David R Hembree: Backside method for fabricating semiconductor components with conductive interconnects. Micron Technology, Stephen A Gratton, July 1, 2008: US07393770 (87 worldwide citation)

A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from t ...


6
William M Hiatt, Warren M Farnworth, Charles M Watkins, Nishant Sinha: Semiconductor component having encapsulated, bonded, interconnect contacts. Micron Technology, Stephen A Gratton, June 14, 2005: US06906418 (76 worldwide citation)

A semiconductor component includes a die having a pattern of die contacts, and interconnect contacts bonded to the die contacts and encapsulated in an insulating layer. The component also includes terminal contacts formed on tip portions of the interconnect contacts. Alternately the component can in ...


7
William M Hiatt: Pass through via technology for use during the manufacture of a semiconductor device. Micron Technology, Kevin D Martin, April 3, 2007: US07199050 (65 worldwide citation)

A method for forming vias which pass through a semiconductor wafer substrate assembly such as a semiconductor die or wafer allows two different types of connections to be formed during a single formation process. One connection passes through the wafer without being electrically coupled to the wafer ...


8
Kyle K Kirby, Salman Akram, David R Hembree, Sidney B Rigg, Warren M Farnworth, William M Hiatt: Microelectronic devices and methods for forming interconnects in microelectronic devices. Micron Technology, Perkins Coie, June 19, 2007: US07232754 (62 worldwide citation)

Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelec ...


9
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Wafer level methods for fabricating multi-dice chip scale semiconductor components. Micron Technology, Stephen A Gratton, June 13, 2006: US07060526 (57 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


10
William M Hiatt, Warren M Farnworth, Charles M Watkins, Nishant Sinha: Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts. Micron Technology, Stephen A Gratton, October 12, 2004: US06803303 (49 worldwide citation)

A semiconductor component includes a die having a pattern of die contacts, and interconnect contacts bonded to the die contacts and encapsulated in an insulating layer. The component also includes terminal contacts formed on tip portions of the interconnect contacts. Alternately the component can in ...



Click the thumbnails below to visualize the patent trend.