1
Scott Remington, William L Martino Jr: Structure and method for improving high speed data rate in a DRAM. Motorola, James L Clingan Jr, December 18, 1990: US04979145 (24 worldwide citation)

A dynamic random access memory has a bit of data selected by a multiplexed address. The row address latches twice as much data as can be selected by the column address which follows the row address. After the column address has been utilized, there is still a one of two selection between two bits of ...


2
Dimitris C Pantelakis, William L Martino Jr, Derrick Leach, Frank A Miller, Wai T Lau: Memory device with fast write recovery and related write recovery method. Motorola, Paul J Polansky, Daniel D Hill, July 7, 1998: US05777935 (19 worldwide citation)

A memory (10) such as a current sensing static random access memory (SRAM) achieves fast write recovery through bit line loads and two additional mechanisms. First, an additional load (252) on shared data lines also becomes active to speed the write recovery process. Second, multiple columns (200, 2 ...


3
William L Martino Jr, Jerry D Moench: Substrate bias voltage regulator. Motorola, Anthony J Sarli Jr, Jeffrey Van Myers, James L Clingan Jr, August 30, 1983: US04401897 (17 worldwide citation)

A substrate bias voltage regulator selectively provides one of two predetermined substrate bias voltage levels in response to a timing signal. The selection of substrate bias voltage level is achieved via a reference generator circuit which provides one of two predetermined reference voltages to a c ...


4
Kichio Abe, William L Martino Jr: Sense line charging system for random access memory. Motorola, Joe E Barbee, August 29, 1978: US04110840 (14 worldwide citation)

A random access memory includes a column of static MOS storage cells. Two sense-write conductors are coupled to each cell in the column. Each sense-write conductor is also coupled, respectively, to a termination MOSFET. The first sense-write conductor of each column of storage cells is coupled by me ...


5
William L Martino Jr, Jerry D Moench: Differential capacitive buffer. Motorola, Anthony J Sarli Jr, Vince Ingrassia, Jeffrey Van Myers, September 22, 1981: US04291246 (9 worldwide citation)

A balanced differential circuit is provided which is useful as an address buffer in digital memories. The circuit is illustrated as a single ended input circuit having complementary outputs. Capacitors are used to couple imbalancing signals into the circuit. Through selective timing of load devices ...


6
Dimitris C Pantelakis, William L Martino Jr, Eric S Powers: Circuit and method for enabling semiconductor device burn-in. Motorola, James L Clingan Jr, February 6, 2001: US06185139 (9 worldwide citation)

An integrated circuit device includes low voltage internal circuitry and a first external pin which receives a first information signal. The first information signal provides operating information within a predetermined voltage range. The device includes a mode detector coupled to the first external ...


7
Scott Remington, William L Martino Jr: Row decoder. Motorola, Anthony J Sarli Jr, Jeffrey Van Myers, James L Clingan Jr, October 28, 1986: US04620299 (7 worldwide citation)

A logic decoder provides a true output signal at a first logic state when selected during an active cycle and during an inactive cycle, and at a second logic state when deselected. The logic decoder also provides a complementary output signal. A word line driver circuit couples decoded address signa ...


8
Ruey J Yu, William L Martino Jr: Clock signal test circuit. Motorola, Anthony J Sarli Jr, Jeffrey Van Myers, James L Clingan Jr, December 9, 1986: US04628253 (6 worldwide citation)

An integrated circuit which has serially connected clock drivers for generating sequential clock signals further includes test circuitry for testing for the occurence of the clock signals. The test circuitry includes a current source for each of the sequential clock signals each of which is enabled ...


9
Scott Remington, William L Martino Jr: Row decoder. Motorola, John A Fisher, Jeffrey Van Myers, James L Clingan Jr, April 28, 1987: US04661724 (3 worldwide citation)

A row decoder includes a logic decoder, a word line driver circuit, and first and second coupling circuits. The logic decoder provides a logic high in an inactive cycle and when selected in an active cycle, and a logic low when deselected in the active cycle. Each of a plurality of word line driver ...