1
Marc Tremblay, William Joy: Efficient handling of a large register file for context switching. Sun Microsystems, Ken J Koestner, Skjerven Morrill MacPherson, March 20, 2001: US06205543 (38 worldwide citation)

A processor including a large register file utilizes a dirty bit storage coupled to the register file and a dirty bit logic that controls resetting of the dirty bit storage. The dirty bit logic determines whether a register or group of registers in the register file has been written since the proces ...


2
Marc Tremblay, William Joy: Multiple-thread processor for threaded software applications. Sun Microsystems, Zagorin O&apos Brien & Graham, April 6, 2004: US06718457 (38 worldwide citation)

A processor has an improved architecture for multiple-thread operation on the basis of a highly parallel structure including multiple independent parallel execution paths for executing in parallel across threads and a multiple-instruction parallel pathway within a thread. The multiple independent pa ...


3
William Joy, Marc Tremblay, Gary Lauterbach, Joseph I Chamdani: Multiple-thread processor with in-pipeline, thread selectable storage. Sun Microsystems, Gunnison McKay & Hodgson L, February 27, 2007: US07185185 (32 worldwide citation)

A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In ve ...


4
Marc Tremblay, William Joy: Apparatus and method for optimizing die utilization and speed performance by register file splitting. Sun Microsystems, Ken J Koestner, Skjerven Morrill MacPherson, January 29, 2002: US06343348 (23 worldwide citation)

A multi-ported register file is typically metal limited to the area consumed by the circuit proportional with the square of the number of ports. A processor having a register file structure divided into a plurality of separate and independent register files forms a layout structure with an improved ...


5
William Joy, Serdar Ergene, Szu Cheng Sun: Apparatus for rapidly switching between frames to be presented on a computer output display. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, August 27, 1991: US05043923 (21 worldwide citation)

A computer output system having a first full screen bitmapped memory, a second full screen bitmapped memory, logic circuitry for providing input signals for writing information to be displayed by an output device to each position of the first memory, logic circuitry for storing in the second memory ...


6
William Van Loo, John Watkins, Robert Garner, William Joy, Joseph Moran, William Shannon, Ray Cheng: Virtual address write back cache with address reassignment and cache block flush. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, December 1, 1998: US05845325 (21 worldwide citation)

Hardware and software improvements in workstations which utilize virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes. In virtual addressing, multi-user workstations, system performance may be i ...


7
William Joy, Robert B Garner: BISC with interconnected register ring and selectively operating portion of the ring as a conventional computer. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, January 21, 1992: US05083263 (20 worldwide citation)

An integer processing unit for a reduced instruction set computer having a plurality of registers arranged in groups referred to as register windows, each window register group including a number of input registers, a similar number of output registers, and a number of local registers, the register ...


8
William Joy, Robert B Garner: Risc processing unit which selectively isolates register windows by indicating usage of adjacent register windows in status register. Sun Microsystems, Blakely Sokoloff Taylor and Zafman, October 27, 1992: US05159680 (16 worldwide citation)

An integer processing unit for a reduced instruction set computer having a plurality of registers arranged in groups referred to as register windows, each window register group including a number of input registers, a similar number of output registers, and a number of local registers, the register ...


9
Marc Tremblay, William Joy: Clustered architecture in a VLIW processor. Sun Microsystems, Zagorin O&apos Brien & Graham, September 2, 2003: US06615338 (12 worldwide citation)

A Very Long Instruction Word (VLIW) processor has a clustered architecture including a plurality of independent functional units and a multi-ported register file that is divided into a plurality of separate register file segments, the register file segments being individually associated with the plu ...


10
Thomas L Lyon, Sun Den Chen, William Joy, Leslie D Kohn, Charles E Narad, Robert Yung: Virtual input/output processor utilizing an interrupt handler. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, March 10, 1998: US05727219 (9 worldwide citation)

A virtual I/O processor (VIOP) is implemented using a programmed I/O (PIO) unit. The PIO unit is complemented by a VIOP interrupt, a VIOP interrupt handler, and a number of VIOP data structures. Preferably, the PIO unit is further complemented with a set of dedicated I/O global registers, a number o ...