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Casper Anthony Scalzi, Eric Mark Schwarz, William John Starke, James Robert Urquhart, Douglas Wayne Westcott: Preprocessing of stored target routines for emulating incompatible instructions on a target processor. International Business Machines Corporation, Marc A Ehrlich, Bernard M Goldman, December 28, 1999: US06009261 (335 worldwide citation)

Provides a program translation and execution method which stores target routines (for execution by a target processor) corresponding to incompatible instructions, interruptions and authorizations of an incompatible program written for execution on another computer system built to a computer architec ...


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Frank Eliot Levine, William John Starke, Edward Hugh Welbon: Method and system for instruction trace reconstruction utilizing limited output pins and bus monitoring. International Business Machines Corporation, Casimer K Salys, Andrew J Dillon, March 2, 1999: US05878208 (35 worldwide citation)

Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timin ...


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Alexander Erik Mericas, William John Starke, Joel M Tendler: Method system and apparatus for instruction tracing with out of order processors. International Business Machines Corporation, Duke W Yee, Mark E McBurney, Lisa L B Yociss, February 17, 2004: US06694427 (33 worldwide citation)

A method, system and apparatus for instruction tracing with out of order speculative processors. With the present invention, information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions fetche ...


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Casper Anthony Scalzi, Eric Mark Schwarz, William John Starke, James Robert Urquhart, Douglas Wayne Westcott: Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation. International Business Machines Corporation, Marc A Ehrlich, Bernard M Goldman, June 13, 2000: US06075937 (31 worldwide citation)

Preprocessing emulation methods utilizing search argument controls for a template routine address table in a target computing system. Target routines are stored in a target computing system for emulating incompatible instructions of an incompatible architecture which need not be recognized by the ar ...


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Robert Alan Cargnoni, Guy Lynn Guthrie, Kirk Samuel Livingston, William John Starke: Cache directory array recovery mechanism to support special ECC stuck bit matrix. International Business Machines Corporation, Casimer K Salys, Jack V Musgrove, September 18, 2007: US07272773 (29 worldwide citation)

A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a ...


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Ravi Kumar Arimilli, Robert Alan Cargnoni, Guy Lynn Guthrie, William John Starke: Data processing system providing hardware acceleration of input/output (I/O) communication. International Business Machines Corporation, Casimer K Salys, Dillon & Yudell, May 16, 2006: US07047320 (27 worldwide citation)

An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication between the pr ...


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Robert Alan Cargnoni, Guy Lynn Guthrie, Kirk Samuel Livingston, William John Starke: Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism. International Business Machines Corporation, Casimer K Salys, Jack V Musgrove, June 27, 2006: US07069494 (24 worldwide citation)

A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a ...


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Robert Alan Cargnoni, Guy Lynn Guthrie, William John Starke: Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members. International Business Machines Corporation, Duke W Yee, Mark E McBurney, February 7, 2006: US06996679 (22 worldwide citation)

A method and apparatus in a data processing system for protecting against displacement of two types of cache lines using a least recently used cache management process. A first member in a class of cache lines is selected as a first substitute victim. The first substitute victim is unselectable by t ...


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Vicente Enrique Chung, Guy Lynn Guthrie, William John Starke, Jeffrey Adam Stuecheli: System bus structure for large L2 cache array topology with different latency domains. International Business Machines Corporation, Diana R Gerhardt, Jack V Musgrove, December 23, 2008: US07469318 (21 worldwide citation)

A cache memory which loads two memory values into two cache lines by receiving separate portions of a first requested memory value from a first data bus over a first time span of successive clock cycles and receiving separate portions of a second requested memory value from a second data bus over a ...



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