1
Mario Macera, William E Jennings, Dennis Josifovich, George W Kajos, John A Mastroianni, Francis E Neil, Victor Bennett, Frank J Bruns, Gururaj Deshpande, Jeremy Greene: System having central processor for transmitting generic packets to another processor to be altered and transmitting altered packets back to central processor for routing. Bay Networks Group, February 6, 1996: US05490252 (415 worldwide citation)

An internetworking system for exchanging packets of information between networks, the system comprising a network interface module for connecting a network to the system, receiving packets from the network in a native packet format used by the network and converting each received native packet to a ...


2
William E Jennings, Roland G Chan, John L Wong: Computer system with cascaded peripheral component interconnect (PCI) buses. Cisco Systems, Elmer Galbi, May 20, 1997: US05632021 (196 worldwide citation)

A system including primary and secondary PCI (Peripheral Component Interconnect) buses which do not "livelock". The system includes two PCI to PCI bridges between the primary and secondary buses. One of the bridges is configured to only act as a target on the primary bus and as a master on the secon ...


3
Michael L Wright, Kenneth Michael Key, Darren Kerr, William E Jennings: System for context switching between processing elements in a pipeline of processing elements. Cisco Technology, Cesari and McKenna, August 8, 2000: US06101599 (87 worldwide citation)

A system and technique facilitate fast context switching among processor complex stages of a pipelined processing engine. Each processor complex comprises a central processing unit (CPU) core having a plurality of internal context switchable registers that are connected to respective registers withi ...


4
Kenneth Michael Key, Michael L Wright, Darren Kerr, William E Jennings: Synchronization and control system for an arrayed processing engine. Cisco Technology, Cesari and McKenna, September 12, 2000: US06119215 (62 worldwide citation)

A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control sy ...


5
Kenneth Michael Key, Michael L Wright, Darren Kerr, William E Jennings, Scott Nellenbach: Parallel processor with debug capability. Cisco Technology, Cesari and McKenna, January 9, 2001: US06173386 (59 worldwide citation)

A parallel processor is provided that includes integrated debugging capabilities. The processor includes a pipelined processing engine, having an array of processing element complex stages, and input and output header buffers. A debug system is provided that, when triggered, may put some or all of t ...


6
Stephen C Hilla, James M Edwards, Timothy F Masterson, William E Jennings: Method and apparatus for generating error detection data for encapsulated frames. Cisco Technology, Cesari and McKenna, May 1, 2001: US06226771 (55 worldwide citation)

An error detection generator calculates error detection data for insertion into encapsulated frames. The error detection generator is configured to calculate multiple error detection values and insert them into corresponding fields of the encapsulated frames. The error detection generator includes a ...


7
Michael L Wright, Darren Kerr, Kenneth Michael Key, William E Jennings: Method and apparatus for passing data among processor complex stages of a pipelined processing engine. Cisco Technology, Ceariand McKenna, February 27, 2001: US06195739 (52 worldwide citation)

A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory ...


8
Darren Kerr, Kenneth Michael Key, Michael L Wright, William E Jennings: Programmable processing engine for efficiently processing transient data. Cisco Technology, Cesari and McKenna, January 28, 2003: US06513108 (45 worldwide citation)

A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units with a plurality of interfaces fr ...


9
Michael L Wright, Darren Kerr, Kenneth Michael Key, William E Jennings: Architecture for a process complex of an arrayed pipelined processing engine. Cisco Technology, Cesari and McKenna, August 27, 2002: US06442669 (41 worldwide citation)

A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context data memory structures via a memory ...


10
Kenneth Michael Key, Michael L Wright, Darren Kerr, William E Jennings: Synchronization and control system for an arrayed processing engine. Cisco Technology, Cesari and McKenna, August 7, 2001: US06272621 (32 worldwide citation)

A synchronization and control system for an arrayed processing engine of an intermediate network station comprises sequencing circuitry that controls the processing engine. The processing engine generally includes a plurality of processing element stages arrayed as parallel pipelines. The control sy ...