1
Neal T Christensen, William C Van Loo, Robert H Werner, Joseph A Wetzel, Carl Zeitler Jr: Multiprocessor mechanism for handling channel interrupts. International Business Machines, Bernard M Goldman, June 2, 1981: US04271468 (97 worldwide citation)

The disclosure relates to multiprocessor handling of plural queues of pending I/O interrupt requests (I/O IRs) in a main storage (MS) shared by plural central processors (CPs). An input/output processor (IOP) inserts I/O IR entries onto the queues in accordance with the type of interrupt. The entrie ...


2
Zahir Ebrahim, Satyanarayana Nishtala, William C Van Loo, Kevin Normoyle, Paul Loewenstein, Louis F Coffin III: Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system. Sun Microsystems, Steven F Caserza, Flehr Hohbach Test Albritton & Herbert, May 18, 1999: US05905998 (81 worldwide citation)

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one ...


3
Zahir Ebrahim, Kevin Normoyle, Satyanarayana Nishtala, William C Van Loo: Fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, July 1, 1997: US05644753 (80 worldwide citation)

A multiprocessor computer system has data processors and a main memory coupled to a system controller. Each data processor has a cache memory. Each cache memory has a cache controller with two ports for receiving access requests. A first port receives access requests from the associated data process ...


4
Satyanarayana Nishtala, Zahir Ebrahim, William C Van Loo, Kevin Normoyle, Leslie Kohn, Louis F Coffin III: Packet switched cache coherent multiprocessor system. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, May 27, 1997: US05634068 (77 worldwide citation)

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. All of the sub-systems inclu ...


5
Zahir Ebrahim, Satyanarayana Nishtala, William C Van Loo, Kevin Normoyle, Paul Loewenstein, Louis F Coffin III: Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, August 5, 1997: US05655100 (76 worldwide citation)

A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one ...


6
William C Van Loo: System for maintaining strongly sequentially ordered packet flow in a ring network system with busy and failed nodes. Sun Microsystems, B NoëL Kivlin, Conley Rose & Tayon PC, May 15, 2001: US06233615 (73 worldwide citation)

A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it p ...


7
Charles E Narad, Zahir Ebrahim, Satyanarayana Nishtala, William C Van Loo, Kevin B Normoyle, Louis F Coffin III, Leslie Kohn: Method and apparatus for reducing power consumption in a computer network without sacrificing performance. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, November 25, 1997: US05692197 (69 worldwide citation)

A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independentl ...


8
Satyanarayana Nishtala, Zahir Ebrahim, William C Van Loo, Paul Loewenstein, Sue K Lee, Louis F Coffin III: Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system. Sun Microsystems, Test Albritton & Herbert Flehr Hohbach, December 3, 1996: US05581729 (67 worldwide citation)

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two ...


9
John Watkins, David Labuda, William C Van Loo: Maintaining data coherency between a central cache, an I/O cache and a memory. Sun Microsystems, Blakely Sokoloff Taylor Zafman, September 21, 1993: US05247648 (64 worldwide citation)

An I/O write back cache memory and a data coherency method is provided to a computer system having a cache and a main memory. The data coherency method includes partitioning the main memory into memory segments, dynamically assigning and reassigning the ownership of the memory segments either to the ...


10
William C Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Leslie Kohn, Louis F Coffin III, Charles E Narad: Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, August 12, 1997: US05657472 (56 worldwide citation)

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two ...