1
David M Fried, William C Leipold, Edward J Nowak: FinFET layout generation. International Business Machines Corporation, John W LaBatt, Hoffman Warnick & D&apos Alessandro, December 9, 2003: US06662350 (245 worldwide citation)

A method and system for generating a set of FinFET shapes. The method and system locate a gate in an FET layout. The set of FinFET shapes is generated coincident with the gate. The method and system can further create a FinFET layout by modifying the FET layout to include the set of FinFET shapes.


2
Orest Bula, Daniel C Cole, Edward W Conrad, William C Leipold: Auto correction of error checked simulated printed images. International Business Machines Corporation, McGinn & Gibb PLLC, Richard M Kotulak Esq, July 23, 2002: US06425112 (197 worldwide citation)

A method and computer system are provided for checking integrated circuit designs for design rule violations. The method may include generating a working design data set, creating a wafer image data set, comparing the wafer image data set to the design rules to produce an error list and automaticall ...


3
Mark A Lavin, William C Leipold: Variable density fill shape generation. International Business Machines Corporation, Howard J Walter Jr, July 13, 1999: US05923563 (57 worldwide citation)

The present invention is directed to a method for adding fill shapes to a chip in a manner which accommodates a wide range of within-chip pattern density variations and provides a tight pattern density control (i) within a chip and (ii) from chip to chip. The present invention imposes a grid over a ...


4
Orest Bula, Daniel C Cole, Edward W Conrad, William C Leipold: Error checking of simulated printed images with process window effects included. International Business Machines Corporation, Richard M Kotulak Esq, McGinn & Gibb PLLC, April 16, 2002: US06373975 (47 worldwide citation)

A structure and method for checking semiconductor designs for design rule violations includes generating a predicted printed structure (i.e., an ideal image) based on the semiconductor designs, altering the ideal image to include potential manufacturing variations, thereby producing at least two pro ...


5
James A Bruce, Orest Bula, Edward W Conrad, William C Leipold: Method of etch bias proximity correction. International Business Machines Corporation, Richard M Kotulak, Connolly Bove Lodge & Hutz, May 28, 2002: US06395438 (23 worldwide citation)

A method for including etch bias corrections in pre-processing of integrated circuit design data to compensate for deviations introduced during lithographic printing and etching. The design data is segmented, and etch bias corrections are applied to the segments based on their proximity to adjacent ...


6
Timothy G Dunham, Ezra D B Hall, Howard S Landis, Mark A Lavin, William C Leipold: Shapes-based migration of aluminum designs to copper damascene. International Business Machines Corporation, Lawrence P Fraley, Schmeiser Olsen & Watts, March 4, 2003: US06528883 (18 worldwide citation)

An interconnect structure for use in semiconductor devices which interconnects a plurality of dissimilar metal wiring layers, which are connected vias, by incorporating shaped voids in the metal layers. The invention also discloses a method by which such structures are constructed.


7
Gary S Ditlow, Daria R Dooling, Timothy G Dunham, William C Leipold, Stephen D Thomas, Ralph J Williams: Autonomic graphical partitioning. International Business Machines Corporation, Gibb I P Law Firm, Richard M Kotulak Esq, May 23, 2006: US07051307 (12 worldwide citation)

Disclosed is a method and structure that partitions an integrated circuit design by identifying logical blocks within the integrated circuit design based on size heuristics of logical macros in the design hierarchy. The invention determines whether the number of logical blocks is within a range of d ...


8
Robert J Allen, John M Cohn, Peter A Habitz, William C Leipold, Ivan L Wemple, Paul S Zuchowski: Simplified tiling pattern method. International Business Machines Corporation, Richard M Kotulek, September 20, 2005: US06948146 (12 worldwide citation)

The invention provides a design and an integrated circuit having a substantially uniform density and electrical characteristics between parts of the IC that are angled at 45 degrees relative to one another. In particular, the invention provides fill tiling patterns oriented substantially uniformly t ...


9
Bette L Bergman Reuter, Mitchell R DeHond, William C Leipold, Daniel N Maynard, Brian D Pfeifer, David C Reynolds, Reginald B Wilcox Jr: Physical design characterization system. International Business Machines Corporation, Richard M Kotulak, November 23, 2004: US06823496 (12 worldwide citation)

A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical des ...


10
James A Bruce, Orest Bula, Edward W Conrad, William C Leipold: Method for edge bias correction of topography-induced linewidth variation. International Business Machines Corporation, Richard M Kotulak Esq, Scully Scott Murphy & Presser, March 25, 2003: US06539321 (12 worldwide citation)

Method for effecting edge bias correction of topography-induced linewidth variations which are encountered in printed or integrated circuits on substrates or semiconductor devices for electronic packages. The method modifies data for current levels which is predicated on prior level data and models, ...