1
James G Gay, William B Ledbetter Jr: Data processing system and method for performing dynamic bus termination. Motorola, Keith E Witek, November 14, 1995: US05467455 (174 worldwide citation)

A data processing system and a method for performing dynamic bus signal termination uses a dynamic bus termination circuitry (14 or 16) with a device (10 or 12). The circuitry is enabled when data is incoming to the device and is disabled when data is outgoing from the device to selectively reduce u ...


2
William B Ledbetter Jr, Russell A Reininger: Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation. Motorola, Robert L King, June 2, 1992: US05119485 (166 worldwide citation)

A bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master. The method and apparatus incorporates an option to source `dirty` or altered data from the write-back cache to the alternate bus master during a memory r ...


3
Robin W Edenfield, William B Ledbetter Jr, Russell A Reininger: System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address. Motorola, Charlotte B Whitaker, October 13, 1992: US05155824 (103 worldwide citation)

A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a ...


4
Steven C McMahan, Kenneth C Scheuer, William B Ledbetter Jr, Michael G Gallup, James G Gay: Data processor having an output terminal with selectable output impedances. Motorola, Robert L King, November 10, 1992: US05162672 (61 worldwide citation)

A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an ...


5
Robin W Edenfield, Ralph McGarity, Russell Reininger, William B Ledbetter Jr, Van B Shahan: Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks varies. Motorola, Charlotte B Whitaker, February 9, 1993: US05185694 (41 worldwide citation)

A block MOVE instruction allows a programmer to issue an instruction to a loosely coupled system bus controller, thereby facilitating the execution of a memory to memory move of multiple data entries, utilizing a burst mode transfer onto the system bus for both reads and writes. The instruction allo ...


6
Robin W Edenfield, William B Ledbetter Jr: Data processor for reloading deferred pushes in a copy-back data cache. Motorola, Charlotte B Whitaker, March 23, 1993: US05197144 (40 worldwide citation)

A data processor is provided for reloading deferred pushes in copy-back cache. When a cache "miss" occurs, a cache controller selects a cache line for replacement, and request a burst line read to transfer the required cache line from an external memory. When the date entries in the cache line selec ...


7
Russell A Reininger, William B Ledbetter Jr, Robin W Edenfield, Van B Shahan, Ralph C McGarity, Eric E Quintana: Memory access serialization as an MMU page attribute. Motorola, Charlotte B Johnson Whitaker, December 24, 1991: US05075846 (37 worldwide citation)

A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independentl ...


8
Russell Reininger, William B Ledbetter Jr: Method for refilling instruction queue by reading predetermined number of instruction words comprising one or more instructions and determining the actual number of instruction words used. Motorola, Charlotte B Whitaker, May 31, 1994: US05317701 (35 worldwide citation)

A sequential prefetch method is provided for a pipelined data processor having a sequential instruction prefetch unit (IPU). An instruction queue in the IPU is coupled to a pipelined instruction unit and an instruction cache of the data processor. A prefetch controller in the IPU keeps the instructi ...


9
Ralph C McGarity, William B Ledbetter Jr, Steven C McMahan, Michael G Gallup, Russell Stanphill, James G Gay: Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation. Robert L King, February 4, 1992: US05086407 (33 worldwide citation)

A single chip data processor integrated circuit having an input which can be programmed to place the circuit's address and data bus terminals into one of two modes. In a first or multiplexed mode, the circuit's address and data terminals are directly connected and address bits are time division mult ...


10
William B Ledbetter Jr, Daniel M McCarthy, James G Gay: Integrated circuit having a control signal for identifying coinciding active edges of two clock signals. Motorola, Keith E Witek, January 16, 1996: US05485602 (28 worldwide citation)

A data processing system receives a CLK signal for performing operations internal to a data processor (10). The data processor (10) has a CPU (12) which performs operations in response to the CLK signal. The bus is allowed to operate at a frequency which is less than or equal to the operational freq ...