1
Chiung Sheng Hsiung, Wen Yi Hsieh, Water Lur: Copper damascene technology for ultra large scale integration circuits. United Microelectronics, Harness Dickey & Pierce, January 16, 2001: US06174812 (205 worldwide citation)

A copper-palladium alloy damascene technology applied to the ultra large scale integration (ULSI) circuits fabrication is disclosed. First, a TaN barrier is deposited over an oxide layer or in terms of the inter metal dielectric (IMD) layer. Then a copper-palladium seed is deposited over the TaN bar ...


2
Wen Yi Hsieh, Tri Rung Yew: Method for forming a DRAM cell electrode. United Microelectronics, November 30, 1999: US05994181 (39 worldwide citation)

A polysilicon layer is subsequently deposited on the dielectric layer by using CVD. Next, photolithography and etching process are used to etch the doped polysilicon layer, and form a bottom electrode of DRAM cell capacitor with U shape in cross section view. The next step of the formation is the de ...


3
Kevin Hsieh, Kun Chih Wang, Wen Yi Hsieh: Deposition method with improved step coverage. United Microelectronics, Harness Dickey & Pierce, April 4, 2000: US06046097 (25 worldwide citation)

A deposition method for improving the step coverage of contact holes is disclosed. The method includes initially placing a semiconductor substrate on a chuck of a chamber, wherein the substrate has some contact holes. The chuck is firstly adjusted and conductive material is firstly deposited onto th ...


4
Kuo Tai Huang, Wen Yi Hsieh, Tri Rung Yew: Method for forming charge storage structure. United Microelectronics, Rabin & Champagne PC, November 30, 1999: US05994183 (21 worldwide citation)

A method for forming a high capacitance charge storage structure that can be applied to a substrate wafer having MOS transistor already formed thereon. The method is to form an insulating layer above the substrate wafer. Next, a contact window exposing a source/drain region is formed in the insulati ...


5
Kuo Tai Huang, Wen Yi Hsieh, Tri Rung Yew: Structure of a capacitor in a semiconductor device having a self align contact window which has a slanted sidewall. United Microelectronics, Thomas Kayden Horstemeyer & Risley, June 20, 2000: US06078492 (21 worldwide citation)

A structure of a capacitor includes two gates and a commonly used source/drain region on a substrate. Then, a pitted self align contact window (PSACW) partly exposes the commonly used source/drain region. Then an glue/barrier layer and a lower electrode of the capacitor are over the PSACW. Then a di ...


6
Michael Wc Huang, Gwo Shii Yang, James CC Huang, Wen Yi Hsieh: Process of forming self-aligned silicide on source/drain region. United Microelectronics, May 29, 2001: US06238989 (20 worldwide citation)

A process of forming a silicide on a source/drain region of a MOS device is described, wherein the MOS device has a gate spacer partially covering the source/drain region. A silicon film is formed on the source/drain region, wherein the silicon film has a portion near the gate spacer substantially t ...


7
Shih Wei Hsiao, Sung Pei Hou, Wen Yi Hsieh: IC socket. Hon Hai Precision, Wei Te Chung, July 14, 2009: US07559784 (16 worldwide citation)

An IC socket includes a socket body with a plurality of contacts disposed therein, a cover rotatablely coupled to the socket body and at least one slider in the socket body. The socket body defines a receiving space for receiving an IC package, and the cover has a driving member. The slider has one ...


8
Hung Yi Huang, Wen Yi Hsieh, Chi Rong Lin, Jenn Tarng Lin: Method of fabricating metal plug. United Microelectronics, Rabin & Champagne PC, April 11, 2000: US06048788 (16 worldwide citation)

A method of forming a metal plug. A contact window is formed to penetrate through a dielectric layer on a substrate having a MOS formed thereon. A titanium glue layer is formed on the dielectric layer and the circumference of the contact window. A titanium barrier layer is formed on the titanium nit ...


9
Wei Chih Lin, Hsiu Yuan Hsu, Wen Yi Hsieh: Burn-in test socket having cover with floatable pusher. Hon Hai Precision, Andrew C Cheng, Wei Te Chung, Ming Chieh Chang, November 9, 2010: US07828576 (15 worldwide citation)

A test socket comprising an insulative base with a plurality of contacts received in the base and a cover pivotally mounted to one end of the base. The cover comprises a pusher with an opening extending therethrough and a lid aligned with the pusher. The lid has a through hole corresponding to the o ...


10
Kun Chih Wang, Ming Sheng Yang, Wen Yi Hsieh: Method fabricating metal interconnected structure. United Microelectronics, Blakely Sokoloff Taylor & Zafman, January 2, 2001: US06169028 (15 worldwide citation)

A method for fabricating a metal interconnect structure. A semiconductor substrate comprising a conductive layer therein is provided. A dielectric layer is formed on the semiconductor substrate. A part of the dielectric layer is removed to form a dual damascene opening and a trench therein, wherein ...