1
Daniel N Tang, Wen Juei Lu: Process for self aligning a source region with a field oxide region and a polysilicon gate. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 9, 1992: US05120671 (48 worldwide citation)

A method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. This method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corne ...


2
Daniel N Tang, Wen Juei Lu: Self-aligned source process and apparatus. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 7, 1992: US05103274 (23 worldwide citation)

A method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. This method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird's beak encroachment and corne ...


3
Bomy Chen, Ying Kit Tsui, Wen Juei Lu: Semiconductor memory array of floating gate memory cells with burried floating gate and pointed channel region. Silicon Storage Technology, DLA Piper Rudnick Gray Cary US, March 29, 2005: US06873006 (15 worldwide citation)

A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetw ...


4
Bomy Chen, Ying Kit Tsui, Wen Juei Lu: Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate and pointed channel region. Silicon Storage Technology, DLA Piper US, April 24, 2007: US07208376 (4 worldwide citation)

A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetw ...


5
Chunming Wang, Baowei Qiao, Zufa Zhang, Yi Zhang, Shiuh Luen Wang, Wen Juei Lu: Method of making a split gate non-volatile floating gate memory cell having a separate erase gate, and a memory cell made thereby. Silicon Storage Technology, DLA Piper, November 17, 2015: US09190532 (1 worldwide citation)

A non-volatile memory cell has a single crystalline substrate of a first conductivity type with a top surface. A first region of a second conductivity type is in the substrate along the top surface. A second region of the second conductivity type is in the substrate along the top surface, spaced apa ...


6
Dana Lee, Wen Juei Lu, Felix Ying Kit Tsui: Landing pad for use as a contact to a conductive spacer. Silicon Storage Technology, DLA Piper, July 6, 2010: US07749779

A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapp ...


7
Chunming Wang, Baowei Qiao, Zufa Zhang, Yi Zhang, Shiuh Luen Wang, Wen Juei Lu: Non-volatile memory cell having a floating gate and a coupling gate with improved coupling ratio therebetween. Silicon Storage Technology, DLA Piper, June 28, 2016: US09379255

A non-volatile memory cell having a split gate, wherein the floating gate and the coupling/control gate have complimentary non-planar shapes. The shape may be a step shape. An array of such cells and a method of manufacturing the cells are also disclosed.


8
Dana Lee, Wen Juei Lu, Felix Ying Kit Tsui: Landing pad for use as a contact to a conductive spacer. Silicon Storage Technology, Ronald L Yin, DLA Piper Rudnick Gray Cary US, November 1, 2005: US06960803

A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapp ...


9
Bomy Chen, Ying Kit Tsui, Wen Juei Lu: Semiconductor memory array of floating gate memory cells with burried floating gate and pointed channel region. Silicon Storage Technology, Gray Cary Ware & Freidenrich, September 23, 2004: US20040183118-A1

A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetw ...


10
Bomy Chen, Ying Kit Tsui, Wen Juei Lu: Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried floating gate and pointed channel region. Dla Piper Rudnick Gray Cary Us, September 15, 2005: US20050199914-A1

A method of forming an array of floating gate memory cells, and an array formed thereby, wherein a trench is formed into a surface of a semiconductor substrate. The source region is formed underneath the trench, the drain region is formed along the substrate surface, and the channel region therebetw ...