1
Watson William J, Stephenson Charles M: Pipelined high speed arithmetic unit. Texas Instruments Incorporated, January 22, 1974: US3787673 (72 worldwide citation)

A digital computer central processing unit is disclosed having an arithmetic unit which forms an element of an instruction processing pipeline. The arithmetic unit has within it a plurality of arithmetic subunits each with its own storage and partitioned on a functional basis for the simultaneous ex ...


2
Cragon Harvey G, Watson William J: Computer memory protection. Texas Instruments Incorporated, April 6, 1971: US3573855 (54 worldwide citation)

A data processing system is provided with a central processing unit with an arithmetic unit which is accessible to and from memory over buffered channels. The system is provided with registers for storage of upper and lower memory bounds for data to be read, data to be written and instructions to be ...


3
Watson William J, Kastner William D: Look-ahead control for operation of program loops. Texas Instruments Incorporated, April 6, 1971: US3573854 (39 worldwide citation)

A look-ahead system for a digital computer is disclosed. This digital computer has programmed instructions stored in and retrievable from a memory. Instruction streams from the memory are passed seriatim through a plurality of instruction registers for processing the instructions. A preliminary deco ...


4
Watson William J, Kastner William D: Automatic context switching in a multiprogrammed multiprocessor system. Texas Instruments Incorporated, October 19, 1971: US3614742 (38 worldwide citation)

An interface between a central processing unit and a peripheral processing unit responds to a program instruction of either system call and proceed or system call and wait. Interfacing interlocking is provided for directing to a reserved address in memory an instruction code developed in the central ...


5
Watson William J, Kastner William D, Cooper Thomas E: Memory buffer for vector streaming. Texas Instruments Incorporated, April 6, 1971: US3573851 (32 worldwide citation)

A data processing system is provided with a central processing unit with an arithmetic unit which is accessible from memory over two buffered channels and accessible to memory over one buffered channel. The central processing unit is provided with a program addressable register file for storage of m ...


6
Watson William J, Husband Edwin H: Variable time slot assignment of virtual processors. Texas Instruments Incorporated, April 6, 1971: US3573852 (30 worldwide citation)

A peripheral processor supporting a central processor is provided with a plurality of virtual processors which utilize one arithmetic unit. A sequencer operating at clock rate assigns to the virtual processors time slots for utilization of the arithmetic unit. An addressable register stores codes re ...


7
Best Dennis R, Watson William J: Distributed priority of access to a computer unit. Texas Instruments Incorporated, April 6, 1971: US3573856 (17 worldwide citation)

Priority of access, as between a plurality of users, to a computer element such as a memory module is controlled by establishing a fixed priority sequence and, in response to each completion of access to such module, shifting the starting point in said fixed priority sequence from one point to anoth ...


8
Watson William J, Husband Edwin H: Open-ended computer with selectable 1/0 control. Texas Instruments Incorporated, March 13, 1973: US3720920 (15 worldwide citation)

An automatic data processing machine of open-ended construction having communication register units in a peripheral process that are addressable by means of a single instruction in the bit, byte, half-word or full-word level for implementing a broad range of I/O operations.


9
Watson William J, Cooper Thomas E: Look-ahead control for operation of program loops. Texas Instruments Incorporated, April 6, 1971: US3573853 (13 worldwide citation)

A programmed computer look-ahead system is responsive to the presence in the instruction stream of a look-ahead instruction which is followed after a predetermined number of instructions by a conditional branch instruction. A decoder responds to the look-ahead instruction to establish an index which ...


10
Watson William J: Dual mode bulk memory extension system for a data processing. Texas Instruments Incorporated, Levine Harold, Grossman Rene E, Devine Thomas G, November 4, 1975: US3918031 (3 worldwide citation)

A dual mode random access bulk memory extension in a first mode is in the address range of central memory and may be directly addressed through a memory control unit. In a second mode blocks of data may be transferred at high speed between the random access bulk memory and central memory.