51
David R Hembree, Warren M Farnworth, Salman Akram, Alan G Wood, C Patrick Doherty, Andrew J Krivy: Probe card for semiconductor wafers and method and system for testing wafers. Micron Technology, Stephen A Gratton, May 9, 2000: US06060891 (124 worldwide citation)

A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card incl ...


52
Lucien J Bissey, Kevin G Duesman, Warren M Farnworth: Annular gate and technique for fabricating an annular gate. Fletcher Yoder, September 21, 2004: US06794699 (123 worldwide citation)

A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gat ...


53
Alan G Wood, Warren M Farnworth, Salman Akram: Method and apparatus for dicing semiconductor wafers. Micron Technology, Stephen A Gratton, May 18, 1999: US05904546 (120 worldwide citation)

A method and apparatus for dicing semiconductor wafers is provided. The method comprises: forming an etch mask on the wafer, and then etching the wafer with a wet etchant, such as KOH, to form a peripheral groove around each die. Etching the wafer can be from the front side of the wafer, from the ba ...


54
Warren M Farnworth, Alan G Wood, Mike Brooks: Semiconductor package including flex circuit, interconnects and dense array external contacts. Micron Technology, Stephen A Gratton, October 15, 2002: US06465877 (120 worldwide citation)

A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in e ...


55
Jerrold L King, Jerry M Brooks, Warren M Farnworth, George P McGill: Semiconductor assembly utilizing elastomeric single axis conductive interconnect. Micron Technology, Wells St John & Roberts, August 18, 1992: US05140405 (117 worldwide citation)

An semiconductor assembly includes at least one die having substantially planar first and second engagement surfaces and external edges which define a die shape. A base having an opening formed therein receives the die. The base opening has peripheral edges which define an opening shape and size whi ...


56
Salman Akram, Warren M Farnworth, Alan G Wood: Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads. Micron Technology, Stephen A Gratton, January 14, 1997: US05592736 (115 worldwide citation)

A method for testing unpackaged semiconductor dice having raised contact locations (e.g., bumped bond pads) and a method for forming an interconnect suitable for testing this type of dice are provided. The interconnect includes a substrate having contact members comprising an array of sharpened elon ...


57
Salman Akram, Warren M Farnworth, David R Hembree: Test system with mechanical alignment for semiconductor chip scale packages and dice. Micron Technolgoy, Stephen A Gratton, January 25, 2000: US06018249 (113 worldwide citation)

A test system for testing semiconductor components, such as bumped dice and chip scale packages, is provided. The test system includes a base for retaining one or more components, and an interconnect for making temporary electrical connections with the components. The test system also includes an al ...


58
Warren M Farnworth, Alan G Wood, Mike Brooks: Stackable semiconductor package having conductive layer and insulating layers and method of fabrication. Micron Technology, Stephen A Gratton, September 17, 2002: US06451624 (113 worldwide citation)

A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive trace ...


59
Warren M Farnworth, David R Hembree: Method for producing laminated film/metal structures for known good die ("KG") applications. Micron Technology, Trask Britt & Rossa, July 7, 1998: US05776824 (109 worldwide citation)

A process for producing laminated film/metal structures comprising bumped circuit traces on a non-conductive substrate wherein a copper sheet/polyimide film laminate is coated with resist on the exterior surfaces. The resist adjacent the polyimide film is selectively exposed and etched to expose an ...


60
Salman Akram, Alan G Wood, Warren M Farnworth: Temporary package, system, and method for testing semiconductor dice and chip scale packages. Micron Technology, Stephen A Gratton, February 13, 2001: US06188232 (107 worldwide citation)

An improved interconnect for semiconductor dice, a method for testing dice using the interconnect, and a method for fabricating the interconnect are provided. The interconnect includes dense arrays of contact members configured to establish temporary electrical communication with contact locations o ...