1
Rick Lake
Warren M Farnworth, Rick C Lake, William M Hiatt: Microfeature workpieces having alloyed conductive structures, and associated methods. Micron Technology, Perkins Coie, January 28, 2014: US08637994

Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a target location of a microfeature workpiece, with the volume of material including at least a first metallic cons ...


2
Rick Lake
Warren M Farnworth, Rick C Lake, William M Hiatt: Microfeature workpieces having alloyed conductive structures, and associated methods. Micron Technology, January 3, 2013: US20130004792-A1

Microfeature workpieces having alloyed conductive structures, and associated methods are disclosed. A method in accordance with one embodiment includes applying a volume of material to a target location of a microfeature workpiece, with the volume of material including at least a first metallic cons ...


3
Warren M Farnworth, Alan G Wood, William M Hiatt, James M Wark, David R Hembree, Kyle K Kirby, Pete A Benson: Multi-dice chip scale semiconductor components and wafer level methods of fabrication. Micron Technology, Stephen A Gratton, January 11, 2005: US06841883 (357 worldwide citation)

A semiconductor component includes a base die and a secondary die stacked on and bonded to the base die. The base die includes conductive vias which form an internal signal transmission system for the component, and allow the circuit side of the secondary die to be bonded to the back side of the bas ...


4
Salman Akram, Alan G Wood, Warren M Farnworth: Single piece package for semiconductor die. Micron Technology, Stephen A Gratton, April 14, 1998: US05739585 (353 worldwide citation)

A method for packaging a bare semiconductor die using a one piece package body with a pattern of external conductors is provided. The package body includes a die mounting location and an interconnect opening that aligns with the bond pads on the die. Electrical interconnects, such as wire bonds, are ...


5
Salman Akram, Alan G Wood, Warren M Farnworth: Stackable chip scale semiconductor package with mating contacts on opposed surfaces. Micron Technology, Stephen A Gratton, January 11, 2000: US06013948 (320 worldwide citation)

A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second cont ...


6
Angus C Fox III, Warren M Farnworth: High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias. Micron Technology, Angus C Fox III, July 7, 1992: US05128831 (319 worldwide citation)

A high-density package containing identical multiple IC chips is disclosed. The package is assembled from submodules interleaved with frame-like spacers. Each submodule comprises a rectangular, wafer-like substrate. The substrate has a planar metalization pattern, comprising conductive traces, on it ...


7
Warren M Farnworth, Alan G Wood, Mike Brooks: Semiconductor package including flex circuit, interconnects and dense array external contacts. Micron Technology, Stephen A Gratton, August 1, 2000: US06097087 (288 worldwide citation)

A chip scale semiconductor package and a method for fabricating the package are provided. The package includes a semiconductor die and a flex circuit bonded to the face of the die. The flex circuit includes a polymer substrate with a dense array of external contacts, and a pattern of conductors in e ...


8
Salman Akram, Alan G Wood, Warren M Farnworth: Method for fabricating stackable chip scale semiconductor package. Micron Technology, Stephen A Gratton, May 22, 2001: US06235554 (284 worldwide citation)

A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second cont ...


9
Salman Akram, Alan G Wood, Warren M Farnworth: Method of producing a single piece package for semiconductor die. Micron Technology, Stephen A Gratton, October 7, 1997: US05674785 (269 worldwide citation)

A method for packaging a bare semiconductor die using a one piece package body with a pattern of external conductors is provided. The package body includes a die mounting location and an interconnect opening that aligns with the bond pads on the die. Electrical interconnects, such as wire bonds, are ...


10
Warren M Farnworth, Alan G Wood, Mike Brooks: Stacked semiconductor package and method of fabrication. Micron Technology, Stephen A Gratton, February 1, 2000: US06020629 (259 worldwide citation)

A semiconductor package and a method for fabricating the package are provided. The package includes multiple substrates in a stacked configuration, each having a semiconductor die mounted thereon. Each substrate includes matching patterns of external contacts and contact pads formed on opposing side ...



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