1
Shivaling S Mahant Shetti, Derek J Smith, Basavaraj I Pawate, George R Doddington, Warren L Bean, Mark G Harward, Thomas J Aton: Distributed processing memory chip with embedded logic having both data memory and broadcast memory. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Richard L Donaldson, May 12, 1998: US05751987 (200 worldwide citation)

Memory chips with data memory (202), embedded logic (206) and broadcast memory (204) for two modes of operation are disclosed. A first mode of operation is the usual memory mode expected of a data RAM. The second mode of operation allows localized computation and/or processing of the data in data me ...


2
Derek Smith, Shivaling Mahant Shetti, Basavaraj Pawate, George R Doddington, Warren L Bean: Devices, systems and methods for implementing a Kanerva memory. Texas Instruments Incorporated, Douglas A Sorensen, Richard L Donaldson, William E Hiller, February 14, 1995: US05390139 (9 worldwide citation)

A memory system 10 is provided including a processor 12 and an active memory device 14 coupled to a processor 12. Active memory 14 includes a first memory 20 for storing a plurality of possible addresses and a second memory 22 for storing an actual address received from processor 12. Circuitry 26 is ...


3
Mahant Shetti Shivaling S, Derek J Smith, Basavaraj I Pawate, Doddington George R, Warren L Bean, Harward Mark G, Thomas J Aton: Integrated circuit. Texas Instr &Lt Ti&Gt, July 26, 1994: JP1994-208501

PURPOSE: To perform parallel processing on a large amount of data by only increasing the number of integrated circuits. CONSTITUTION: An integrated circuit is provided with a data memory 202 connected to a data bus terminal, a multiaddress communication memory 204 connected to the data bus terminal, ...